Bizarre Patents
Neuroimaging as a Marketing Tool
Neuroimaging as a means for validating whether a stimulus such as advertisement, communication, or product evokes a certain mental response such as emotion, preference, or memory, or to predict the consequences of the stimulus on later behavior such as consumption or purchasing.
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| Number | Title | Issue Date |
| 7116739 | Auto baud system and method and single pin communication interface In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits cou... | 10/03/2006 |
| 7117319 | Managing processor architected state upon an interrupt A method and system are disclosed for managing a hard architected state of a processor that is critical for executing a process in the processor. A shadow copy of the hard architected state is stored from the processor to memory when an interrupt is received by the ... | 10/03/2006 |
| 7117353 | Methods and apparatus to enable console redirection in a multiple execution environment Methods and apparatus to enable console redirection in a multiple execution environment are disclosed. In an example method, at least one periodic interrupt in a first basic input/output system (BIOS) execution environment of a local console is initiated. Data assoc... | 10/03/2006 |
| 7113995 | Method and apparatus for reporting unauthorized attempts to access nodes in a network computing system A method in a node for managing authorized attempts to access the node. A packet is received from a source, wherein the packet includes a first key. A determination is made as to whether the first key matches a second key for the node. The packet is dropped without ... | 09/26/2006 |
| 7114022 | Method for generating interrupt signal and media access controller utilizing the same A method for generating an interrupt signal for a media access controller (MAC) in communication with a computer host and an external network is disclosed. The method includes steps of asserting an interrupt signal to the computer host when at least one data packet ... | 09/26/2006 |
| 7114039 | Signal processor with a plurality of kinds of processors and a shared memory accessed through a versatile control means A signal processor comprises a plurality of processing circuits for carrying out various kinds of processing which differ from one another; a memory circuit provided commonly for respective processing circuits, and a control circuit for carrying out access control b... | 09/26/2006 |
| 7111157 | Spurious input detection for firmware A system and method for detecting and handling spurious input are disclosed. In one embodiment, upon receipt of an interrupt signal, a device activates command and keystroke timeouts. The keystroke timeout may have a shorter duration than the command timeout and may... | 09/19/2006 |
| 7111089 | Programmable scheduler for digital signal processor A digital signal processor operates in conjunction with a scheduler hardware module and a scheduler software module in executing a highest priority runnable event among a plurality of events. The scheduler hardware module communicates an interrupt request signal to ... | 09/19/2006 |
| 7106943 | Coding device, coding method, program and recording medium A coding device includes: a decoder for decoding a first stream signal in which a first video stream including a first video stream information generated by coding a first video signal and a first audio stream including a first audio stream information generated by ... | 09/12/2006 |
| 7107363 | Microprocessor having bandwidth management for computing applications and related method of managing bandwidth allocation The present invention discloses, in one aspect, a microprocessor. In one embodiment, the microprocessor includes a processing element configured to process an application using a bandwidth. The microprocessor also includes an access shaper coupled to the processing ... | 09/12/2006 |
| 7107374 | Method for bus mastering for devices resident in configurable system logic A processor is connected to a configurable system interconnect (CSI) bus. A CSL is connected to the CSI bus. The CSL comprises a first set of signal lines to send a data transfer request and a second set of signal lines to receive a grant associated with the data tr... | 09/12/2006 |
| 7107494 | Bus architecture using debug packets to monitor transactions on an internal data processor bus A processing system comprising: i) processor core; ii) a memory; iii) N peripheral devices; and iv) a communication bus coupled to the processor core, the memory and the N peripheral devices that transfers bus request packets between the processor core, the memory, ... | 09/12/2006 |
| 7107587 | Access redirector and entry reflector When using a common configuration data structure (e.g., “registry”), the access redirector and entry reflector promotes compatibility and interoperability between differing versions of program modules. The access redirector redirects selected accesses to storage... | 09/12/2006 |
| 7107439 | System and method of controlling software decompression through exceptions When processor instructions are required for execution, a misaligned address is sent to the processor. The misaligned instruction address causes a computer processor exception. The computer system automatically executes an exception handling routine that transforms ... | 09/12/2006 |
| 7103703 | Back to back connection of PCI host bridges on a single PCI bus Duplicate PCI bridge devices are configured for synchronous initializations based on shared initialization signals. A first of the PCI bridge devices is configured to rely on bus arbitration performed by the second PCI bridge device. The first PCI bridge device also... | 09/05/2006 |
| 7103761 | Server system with multiple management user interfaces A cPCI server system includes a plurality of printed circuit assemblies, including at least one host processor card. A server management card is coupled to the plurality of printed circuit assemblies for monitoring and managing operation of the server system. The se... | 09/05/2006 |
| 7103692 | Method and apparatus for an I/O controller to alert an external system management controller Embodiments of the present invention provide a method and apparatus to allow an I/O controller to alert an external controller using an enhanced SMBus implementation that enables bi-directional capability on SMBALERT#. I/O controller includes an auxiliary control re... | 09/05/2006 |
| 7103693 | Method for applying interrupt coalescing to incoming messages based on message length A balanced approach is provided for interrupt coalescing, wherein interrupts of locking and other small size packets are maximized, while large data segment interrupts are minimized. Thus, the most desirable interrupt characteristics of both large data segments and ... | 09/05/2006 |
| 7103763 | Storage and access of configuration data in nonvolatile memory of a logically-partitioned computer An apparatus, program product and method utilize a nonvolatile solid state memory organized so as to store variable amounts of configuration data for a logically-partitioned computer in an efficient, compact and cost-effective manner. A nonvolatile solid state memor... | 09/05/2006 |
| 7103766 | System and method for making BIOS routine calls from different hardware partitions The specification may disclose systems and related methods for ensuring that as between two partitions in a computer system, each partition using a separate operating system, calls to basic input output system (BIOS) routines are managed in such a way that only one ... | 09/05/2006 |
| 7103268 | Optical disk reproducer The number of sectors which are NV_PCK in an ECC block is detected by a number-of-sectors detection circuit 12, and a control circuit 14 considers, when the detected number of sectors is larger than a predetermined value, that NV_PCK reference processi... | 09/05/2006 |
| 7103691 | Method, system and device for a processor to access devices of different speeds using a standard memory bus A method for accessing a device, such as a memory device and an interface device, by a processor is disclosed. The method involves the processor requesting access permission for the transfer of data. The bridge device grants access permission. The processor in respo... | 09/05/2006 |
| 7103128 | Data synchronization circuit and communication interface circuit There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for holding the bus data which is synchronous with the first clock and is inpu... | 09/05/2006 |
| 7103823 | Communication between multi-processor clusters of multi-cluster computer systems Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnec... | 09/05/2006 |
| 7099978 | Method and system of completing pending I/O device reads in a multiple-processor computer system A method and system for completing pending I/O device reads by periodically stalling the issuance of I/O device accesses by a program in a multiple-processor computer system. ... | 08/29/2006 |
| 7100027 | System and method for reproducing system executions using a replay handler Methods and systems for replaying arbitrary system executions are disclosed. A system includes a storage element, a memory hierarchy and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The proces... | 08/29/2006 |
| 7099977 | Processor interrupt filtering A method for processing an interrupt message in a system having a plurality of processors arranged into at least two partitions. The interrupt message is decoded to identify an interrupt source. If the interrupt source is not in an interrupt set, the interrupt is dr... | 08/29/2006 |
| 7100032 | Method and apparatus for identifying hardware compatibility and enabling stable software images An approach to selecting either an actual stepping revision ID value or a compatible revision ID value to be readable by a processor through a revision ID register. ... | 08/29/2006 |
| 7099984 | Method and system for handling interrupts and other communications in the presence of multiple processing sets A computing system comprises two or more processing sets, for example for fault tolerant operation. The multiple processing sets have a connection to at least one device, typically many devices. The ownership of each device is allocated to one of the two or more pro... | 08/29/2006 |
| 7099955 | End node partitioning using LMC for a system area network A method for routing System Area Network (SAN) packets to multiple partitions within a single end node is provided. A range of Local Identification addresses (LIDs) are assigned to a channel adapter port within the SAN. Lower order bits within the LID are then assig... | 08/29/2006 |
| 7099963 | Method and system for monitoring embedded disk controller components A history module for monitoring plural components in an embedded disk controller with a first main processor operationally coupled to a first bus and a second processor operationally coupled to a second bus is provided. The history module includes an event control m... | 08/29/2006 |
| 7096289 | Sender to receiver request retry method and apparatus Disclosed is a method for and an apparatus using various factors including system performance feedback data to optimize the time suggested to attempt retry of a request. Among the factors used there is included present system performance, type of request, status of ... | 08/22/2006 |
| 7096290 | On-chip high speed data interface An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when receiving a request that requires a response. The first circuit unit ca... | 08/22/2006 |
| 7096472 | Systems and methods for ensuring atomicity of processes in a multitasking computing environment In the present invention, a computer in which a plurality of programs are executed under a management of an Operation System having a memory management mechanism includes a unit for ensuring atomicity of a first user process without requiring a dedicated CPU instruc... | 08/22/2006 |
| 7096294 | Method and computer program product for graphically providing interrupt request (IRQ) routing information A method and an associated computer program product are provided for obtaining interrupt requests (IRQ) routing information in a more efficient and intuitive manner. In this regard, a graphical representation of the routing of a plurality of IRQs capable of being as... | 08/22/2006 |
| 7096295 | Method and device for generating program interruptions in users of a bus system, and bus system A method and device and a bus system for generating at least one program interruption in at least one user of a bus system, at least one user storing a specifiable time value in at least one memory and the time value being compared with at least one base time, the a... | 08/22/2006 |
| 7096296 | Supercharge message exchanger A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM... | 08/22/2006 |
| 7093039 | Communication terminal increasing effective data rate on asynchronous transmission and a data transmission method therefor A UART sets a predetermined threshold remaining data amount n, which defines an interrupt position, in a transmission trigger detector before data transmission is completed, checks if a trigger, which indicates the value of a read pointer RP or a count value N has r... | 08/15/2006 |
| 7093043 | Data array having redundancy messaging between array controllers over the host bus A data array system, and inter-controller-link messaging method, for controlling redundant access to a storage device and providing inter-controller communication without a dedicated controller link. The host has a host bus, such as a PCI bus, and the system include... | 08/15/2006 |
| 7093035 | Computer system, control apparatus, storage system and computer device A computer system which enables more efficient use of a storage system shared by plural host computers and optimizes the performance of the whole system including the host computers and storages. A computer device has a first control block which logically partitions... | 08/15/2006 |
