Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
PatentStorm News
Make the Most of PatentStorm
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest patents by subscribing to an RSS feed.
Got questions? Ask a Patent Expert!
Registered users: Manage your profile, comments and alerts.
| Number | Title | Issue Date |
| 7680972 | Micro interrupt handler A system and method is provided for improved interrupt handling via a micro interrupt handler. Upon an interrupt signal being sent to a processor running a task, a first part of the running task is stored to system memory via direct memory access. A micro interrupt ... | 03/16/2010 |
| 7680973 | Sideband signal for USB with interrupt capability The invention provides for a sideband signal for the USB that has real-time interrupt capabilities. A system and method for hardware detection of an interrupt signal provides for the ability to superimpose a high frequency interrupt signal on a USB power line for tr... | 03/16/2010 |
| 7657683 | Cross-thread interrupt controller for a multi-thread processor An interrupt controller for a dual thread processor has for a first thread, an interrupt request register accessible to the second thread, an interrupt count accessible to the second thread, and an interrupt acknowledge accessible to the first thread. Additionally, ... | 02/02/2010 |
| 7644214 | Information processing apparatus and task execution method An even-driven interrupt processing is efficiently carried out in a multiprocessor system. A main control unit 112 executes a main process as a processing for controlling an apparatus in a unified manner. A sub-control unit 116 executes a task assigned... | 01/05/2010 |
| 7624215 | Interrupt controller An interrupt controller for managing interrupt requests comprises interrupt control circuitry in a first domain, the first domain being switchable to a low-power mode, and interrupt request monitoring circuitry in a second domain. The interrupt control circuitry is ... | 11/24/2009 |
| 7617345 | Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, where... | 11/10/2009 |
| 7613860 | Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, where... | 11/03/2009 |
| 7610425 | Approach for managing interrupt load distribution A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the processors that results from an initial mapping of the interrupts to the proces... | 10/27/2009 |
| 7606958 | Interrupt control method, interrupt control apparatus and interrupt control medium Once accepting an interrupt, the control is such as to not accept any interrupt including that highest priority within the group to which the interrupt about to be processed belongs by referring to the interrupt management table. Then the vector number for the highe... | 10/20/2009 |
| 7587544 | Extending secure digital input output capability on a controller bus Embodiments of techniques for simultaneously connecting a plurality of expansion cards to a single bus of a host controller are described. ... | 09/08/2009 |
| 7581051 | Method for delivering interrupts to user mode drivers Systems and methods for providing a framework within which device drivers may run at a user-mode level. A platform (e.g., APIC) or bus (PCI bus) generic feature is used to take the CPU out of interrupt mode without having to wait for a user-level driver to clear the... | 08/25/2009 |
| 7565471 | Message signaled interrupt extended (MSI-X) auto clear and failsafe lock A method and apparatus is disclosed for improving the MSI and MSI-X specifications by implementing an efficient delivery and clearing mechanism for interrupt conditions to increase performance between the driver and hardware/firmware interface while ensuring that no... | 07/21/2009 |
| 7558897 | Method for adopting an orphan I/O port in a redundant storage controller A method for adopting an orphaned I/O port of a storage controller is disclosed. The storage controller has first and second redundant field-replaceable units (FRU) for processing I/O requests and a third FRU having at least one I/O port for receiving the I/O reques... | 07/07/2009 |
| 7552260 | Method for dynamically arranging interrupt pins A method for dynamically arranging interrupt pins is provided, which is suitable for arranging a plurality of interrupt pins of a control chip. In this method, a number of interrupts sent from each of a plurality of device paths in a unit time is detected. The devic... | 06/23/2009 |
| 7543095 | Managing input/output interruptions in non-dedicated interruption hardware environments Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. Th... | 06/02/2009 |
| 7533207 | Optimized interrupt delivery in a virtualized environment Various operations are disclosed for improving the operational efficiency of interrupt handling in a virtualized environment. A virtualized interrupt controller may obviate the need for an explicit end-of-interrupt command by providing an automatic EOI capability ev... | 05/12/2009 |
| 7529875 | Assigning interrupts for input/output (I/O) devices among nodes of a non-uniform memory access (NUMA) system Assigning interrupts for I/O devices among the nodes of NUMA systems is disclosed. At least one of the following is performed. First, interrupts for the devices are assigned among the nodes based on at least one of: the nodes to which the devices are connected, the ... | 05/05/2009 |
| 7516260 | Method of communicating with embedded controller A method of communicating with an embedded controller is disclosed. The method is adapted for an Advanced Configuration and Power Interface specification (ACPI). According to the method, a busy flag is set in the status register of the embedded controller. While the... | 04/07/2009 |
| 7493435 | Optimization of SMI handling and initialization A method and apparatus for efficient memory allocation and system management interrupt (SMI) handling is herein described. Upon waking a second processor in a multiple processor system, one may use a single SMI to initialize each processor, may use the location of a... | 02/17/2009 |
| 7493436 | Interrupt handling using simultaneous multi-threading Disclosed are a method, information processing system, and computer readable medium for managing interrupts. The method includes placing at least one physical processor of an information processing system in a simultaneous multi-threading mode. At least a first logi... | 02/17/2009 |
| 7454547 | Data exchange between a runtime environment and a computer firmware in a multi-processor computing system A method, system, apparatus, and computer-readable medium for exchanging data between an application program and a firmware in a computer system having multiple CPUs are provided. According to the method, an application program stores an input parameter for the firm... | 11/18/2008 |
| 7454548 | Managing input/output interruptions in non-dedicated interruption hardware environments, and methods therefor Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. Th... | 11/18/2008 |
| 7447820 | Retargeting of platform interrupts Systems, methods, and apparatus to retarget platform interrupts in a reconfigurable system. Some embodiments include identifying each processor of a multiprocessor system capable of processing Corrected Platform Error Interrupts, adding each processor capable of pro... | 11/04/2008 |
| 7447818 | System and method for controlling remote console functionality assist logic A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality assist logic structure for effectuating the sending and receiving of sign... | 11/04/2008 |
| 7447819 | Information processing apparatus and SMI processing method thereof An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an S... | 11/04/2008 |
| 7444450 | Method and system for detecting excessive interrupt processing for a processor A method and system is provided for detecting excessive interrupt processing for a processor. The method includes the operation of defining an interrupt processing period during which measuring of interrupts for a processor takes place. The amounts of time being spe... | 10/28/2008 |
| 7444639 | Load balanced interrupt handling in an embedded symmetric multiprocessor system In an embedded symmetric multiprocessor (ESMP) system it is desirable to maintain equal central processing unit load balance. When an interrupt occurs, a single central processing receives the interrupt and then passes information to the central processing unit sche... | 10/28/2008 |
| 7444449 | Method, computer program product and computer system for controlling execution of an interruption routine A method, a computer program product and a computer system for controlling the execution of an interruption routine for interrupting an active application. The computer system may include a first detector unit operable to detect if any application of multiple other ... | 10/28/2008 |
| 7444385 | Global interrupt and barrier networks A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous... | 10/28/2008 |
| 7441076 | Data storage apparatus that appropriately revises FDCB information during background formatting A data storage apparatus, including a controller that formats a rewritable recording medium in the background, interrupts the background formatting when a host computer requests to store data in the rewritable recording medium, stores the data in the rewritable reco... | 10/21/2008 |
| 7433985 | Conditional and vectored system management interrupts An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is bro... | 10/07/2008 |
| 7434224 | Plural operating systems having interrupts for all operating systems processed by the highest priority operating system Multiple different operating systems are enabled to run concurrently on the same computer. A first operating system is selected to have a relatively high priority (the realtime operating system, such as C5). At least one secondary operating system is selected to hav... | 10/07/2008 |
| 7430629 | Internet SCSI communication via UNDI services A method and system for emulating a hardware Internet Small Computer System Interface (iSCSI) Host Bus Adapter (HBA) without risking an interruption of communication between a computer and a remote secondary storage device is presented. During normal operations, a (... | 09/30/2008 |
| 7428609 | Method and system to partition hardware resources between operating systems Disclosed is a method and system to partition hardware resources between operating systems. A determination is made whether a first PCI resource attached to a line of a bus is to be sequestered to a service operating system (OS). If so, the first PCI resource is seq... | 09/23/2008 |
| 7426728 | Reducing latency, when accessing task priority levels One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is received to write an interrupt mask value to the TPR, and the interrupt ... | 09/16/2008 |
| RE40497 | Communication system which dynamically switches sizes of sample buffer between first size for quick response time and second size for robustness to interrupt latency An apparatus for and method of implementing a novel buffer ba full duplex communication system is disclosed. The disclosed invention is particularly useful in native sign processing systems wherein heavy contention of processor resources typically exist, such as in ... | 09/09/2008 |
| 7421431 | Providing access to system management information System management information may be obtained from multiple input devices associated with system management mode drivers during pre-boot and during runtime of an operating system. The system management information may be converted to a form for presentation manageme... | 09/02/2008 |
| 7421527 | Transmission apparatus and transmission method A small-sized and low-cost transmission apparatus and a transmission method (having a high responsivity) capable of transmitting an interrupt signal with a small number of input/output terminals (without a dedicated line for interrupt signals) are provided. A first ... | 09/02/2008 |
| 7418555 | Multiprocessor system and method to maintain cache coherence A multiprocessor system may have a plurality of processors and a memory unit. Each of the processors may include at least one cache memory. The memory unit may be shared by two of the processors. The multiprocessor system may further include a control unit. If the m... | 08/26/2008 |
| 7415557 | Methods and system for providing low latency and scalable interrupt collection A method for processing an interrupt signal within a microprocessor based system is described. The method includes storing a received interrupt signal within an interrupt cause register of an interrupt controller, outputting an interrupt command from the interrupt c... | 08/19/2008 |