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"That’s an amazing invention, but who would ever want to use one of them?"
President Rutherford B. Hayes ; Said in 1876, after Alexander Graham Bell demonstrated the telephone to him at the White House
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| Number | Title | Issue Date |
| 8051222 | Concatenating secure digital input output (SDIO) interface An apparatus and a process for transferring packet data includes receiving packets from a first interface such as a network interface and transferring data to a second interface such as an SD Bus interface such as SDIO using a protocol such as one described in SDCar... | 11/01/2011 |
| 8041852 | System and method for using a shared buffer construct in performance of concurrent data-driven tasks A computer system is provided that utilizes a buffer construct to manage memory access operations to a region of memory. The buffer construct may correspond to a data item or structure that represents a region of memory. Each task may control the buffer construct ex... | 10/18/2011 |
| 7949801 | Main processor initiating command timing signal via DMA to coprocessor in order to synchronize execution of instructions Coprocessor systems for using a main microprocessor DMA channel to write to a port to control a coprocessor system are provided. In certain examples, coprocessor systems are described using a main CPU counter to trigger a DMA channel to perform a single byte transfe... | 05/24/2011 |
| 7886085 | Removable memory device, phase synchronizing method, phase synchronizing program, medium recording the same, and host terminal An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: ... | 02/08/2011 |
| 7870310 | Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count poin... | 01/11/2011 |
| 7472207 | Optimized-incrementing, time-gap defect detection apparatus and method Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the pro... | 12/30/2008 |
| 7444441 | Device including means for transferring information indicating whether or not the device supports DMA A device for attachment to a host for serial data communication including means for transferring to the host a predetermined data structure indicating whether or not the device supports direct memory access. ... | 10/28/2008 |
| 7441054 | Method of accessing internal memory of a processor and device thereof A method of accessing internal memory of a processor and the device thereof. The method employs a bank swapping mechanism for the processing unit of a processor and a direct memory access controller to simultaneously access different memory units in internal memory.... | 10/21/2008 |
| 7437487 | Storage medium array controller, a storage medium array apparatus, a storage medium drive, a method of controlling a storage medium array, and a signal-bearing medium embodying a program of a storage medium array controller A storage medium drive is controllable by a storage medium array controller. the storage medium array controller receives a data storage medium drive information and the storage medium array controller sets a data transmission parameter with respect to the storage m... | 10/14/2008 |
| 7404015 | Methods and apparatus for processing packets including accessing one or more resources shared among processing engines Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets... | 07/22/2008 |
| 7389365 | Arbitrating and servicing polychronous data requests in direct memory access Systems for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices... | 06/17/2008 |
| 7383363 | Method and apparatus for interval DMA transfer access A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from writing data to a memory until the memory access controller receives a pe... | 06/03/2008 |
| 7380115 | Transferring data using direct memory access A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the prima... | 05/27/2008 |
| 7380027 | DMA controller and DMA transfer method A DMA channel data quantity setting section sets a data transfer quantity of each of a plurality of DMA channels in accordance with a data quantity or a ratio in advance. A channel select control circuit determines whether each DMA channel is active. A data transfer... | 05/27/2008 |
| 7376762 | Systems and methods for direct memory access A system and method for providing direct memory access is disclosed. In a particular embodiment, a direct memory access module is disclosed that includes a memory, a first interface coupled to a processor, and a second interface coupled to a peripheral module. A fir... | 05/20/2008 |
| 7363474 | Method and apparatus for suspending execution of a thread until a specified memory access occurs Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. S... | 04/22/2008 |
| RE40261 | Apparatus and method of partially transferring data through bus and bus master control device A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data items to be transferred while the first device is occupying the bus; d... | 04/22/2008 |
| 7359996 | Data transfer control device, electronic equipment, and data transfer control method Pipe regions PIPE0 to PIPEe (or endpoint regions) are allocated in a packet buffer, registers in which are set page sizes MPS0 to MPe (maximum packet size) and numbers of pages BP0 to BPe for the pipe regions are provided, and data is transferre... | 04/15/2008 |
| 7340554 | USB host controller with DMA capability An embedded host controller, for use in a USB system comprising a processor and an associated system memory, comprises a DMA controller, and the host controller is adapted such that, in order to retrieve data from the associated system memory, a starting address and... | 03/04/2008 |
| 7333519 | Method of manually fine tuning audio synchronization of a home network A method is provided for manually synchronizing the playback of a digital audio broadcast on a plurality of network output devices. The method is applicable for use with methods such as those that use a time code, insert a control track pulse, or use an audio wavefo... | 02/19/2008 |
| 7325119 | Data storage apparatus capable of storing data stored in external equipment In a PVR, when a prescribed type of data is present in external equipment connected to the PVR via an external connection portion, the prescribed type of data is read from the external equipment, and the read data is stored in an HDD. The prescribed type of data sto... | 01/29/2008 |
| 7321451 | Data converting circuit, data converting method, and image forming apparatus A data converting circuit to receive an input data and convert the input data into an output data is disclosed. An output data group corresponding to the value of the input data is stored beforehand in an output data table. A multiplexer receives the input data and ... | 01/22/2008 |
| 7305499 | DMA controller for controlling and measuring the bus occupation time value for a plurality of DMA transfers The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a d... | 12/04/2007 |
| 7302699 | Logged-in device and log-in device A management agent ME1 of a target T1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T1 reaches a predetermined allowable number of simultaneous lo... | 11/27/2007 |
| 7259876 | Image processing apparatus, and, control method and control device therefor A first storage stores input image data. A second storage stores image data read from the first storage. A control part determines, with respect to a timing at which data transfer of image data into the first storage, a data transfer of the said image data from the ... | 08/21/2007 |
| 7249203 | Programmatic time-gap defect detection apparatus and method Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the pro... | 07/24/2007 |
| 7240129 | DMA controller having programmable channel priority A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second me... | 07/03/2007 |
| 7237216 | Clock gating approach to accommodate infrequent additional processing latencies A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal... | 06/26/2007 |
| 7219169 | Composite DMA disk controller for efficient hardware-assisted data transfer operations In one embodiment, a direct memory access (DMA) disk controller used in hardware-assisted data transfer operations includes command receiving logic to receive a data transfer command issued by a processor. The data transfer command identifies one or more locations i... | 05/15/2007 |
| 7209979 | Storage processor architecture for high throughput applications providing efficient user data channel loading A storage processor particularly suited to RAID systems provides high throughput for applications such as streaming video data. An embodiment is configured as an ASIC with a high degree of parallelism in its interconnections. The communications architecture provides... | 04/24/2007 |
| 7209995 | Efficient connection between modules of removable electronic circuit cards A removable electronic circuit card has multiple modules connected to the card's bus in parallel so that each module can exchange commands and data independently with the host. According to a first aspect of the present invention, this achieved by a controller-to-co... | 04/24/2007 |
| 7209998 | Scalable bus structure A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address informa... | 04/24/2007 |
| 7190675 | Adaptive access control in LAN relaying apparatus In a LAN relaying apparatus, a reception side control circuit receives a reception side write pointer from a reception side write control circuit and a reception side read pointer from a reception side read control circuit, and determines a reception side pointer di... | 03/13/2007 |
| 7180732 | Mounting apparatus for storage devices A method and apparatus for mechanically mounting and electrically connecting a plurality of small form factor (SFF) storage devices such as 2.5″ hard disk drives in place of a larger SFF hard disk drive such as a single SFF 3.5″ hard disk drive. This provides in... | 02/20/2007 |
| 7164425 | Method and system for high speed network application A method and system for monitoring frame flow in a Fiber Channel network is provided. The method includes, deleting fill words before any frame data is allowed to be stored in a buffer memory; storing only certain primitive signals and/or frame data in the buffer me... | 01/16/2007 |
| 7162564 | Configurable multi-port multi-protocol network interface to support packet processing A network interface between an internal bus and an external bus architecture having one or more external buses includes an external interface engine and an internal interface. The external interface engine (EIE) is coupled to the external bus architecture, where the... | 01/09/2007 |
| 7159060 | PCI standard hot-plug controller (SHPC) with user programmable command execution timing According to embodiments of the present invention, a peripheral component interconnect (PCI) standard hot-plug controller (SHPC) includes a command register to store PCI slot operation commands for one or more target PCI slots and a programmable register that may be... | 01/02/2007 |
| 7152132 | Method and apparatus for improving buffer utilization in communication networks A method and a switch element for buffer utilization in a network are provided. The method includes, receiving plural frames in a first buffer, if the received frames are less than a full size frame and can be accommodated in the first buffer; sending an available b... | 12/19/2006 |
| 7148763 | Integrated circuit including processor and crystal oscillator emulator An integrated circuit comprises a first circuit that receives a clock signal. A first temperature sensor senses a first temperature. Non-volatile memory that communicates with the first temperature sensor outputs calibration data as a function of the first temperatu... | 12/12/2006 |
| 7146451 | PCI bridge and data transfer methods A bridge for interconnecting a processor to a peripheral device by way of a PCI bus may have a read buffer. The bridge autonomously requests data from the peripheral device and places received data in the read buffer. The processor reads the data from the receive bu... | 12/05/2006 |
