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| Number | Title | Issue Date |
| 6681285 | Memory controller and interface A memory controller is provided that has an access priority arbiter having a memory address bus and a memory data bus for connection with one or more memories and a plurality of requester buses, each for connection to a memory requester. It also has a RAM... | 01/20/2004 |
| 6681279 | Method of performing bus arbitration between control chips in a chipset with preemptive capability A method is proposed for the purpose of performing bus arbitration between two control chips in a chipset with preemptive capability. The two control chips can be, for example, a North Bridge chip and a South Bridge chip, of which one is set as bus owner ... | 01/20/2004 |
| 6678773 | Bus protocol independent method and structure for managing transaction priority, ordering and deadlocks in a multi-processing system A multi-processing system (50) utilizes an interconnect fabric (59) for coupling endpoint devices (52, 54, 56, 66, 67). Bus control functions are managed in a method which is bus protocol independent. Each of the endpoint devices and the fabric function b... | 01/13/2004 |
| 6676022 | Smart card system with command queuing A smart card-based information processing system capable of compatibly operating under a standard requiring the complete processing of one command at a time, but which is also capable of queuing commands received from applications external to the smart ca... | 01/13/2004 |
| 6675268 | Method and apparatus for handling transfers of data volumes between controllers in a storage environment having multiple paths to the data volumes In a storage environment or storage area network having multiple host devices and at least one storage array, the host devices access logical data volumes stored on the storage array through array controllers disposed in the storage array. Multiple host d... | 01/06/2004 |
| 6675246 | Sharing arbiter The Sharing arbiter is an arbiter which, under certain conditions, permits two or more Done signals to be received before the Sharing arbiter issues a grant signal and, under certain conditions, is permitted to issue more than one grant signal before rece... | 01/06/2004 |
| 6671784 | System and method for arbitrating access to a memory A method and a system for arbitrating accesses to a memory in a data processing system having many memory access units (MAU) and an arbiter are disclosed. The arbiter initially sends a permission signal to each MAU to give each MAU a chance to reset its p... | 12/30/2003 |
| 6671761 | Bus system A bus system is provided. The bus system includes: an arbiter that receives access commands output from the plurality of master devices and outputs the access commands in an order according to a predetermined arbitration algorithm; an execution scheduler ... | 12/30/2003 |
| 6665760 | Group shifting and level shifting rotational arbiter system An arbiter system comprises a plurality of hardware resources, a common resource, and an arbiter. The plurality of hardware resources are divided into groups of hardware resources and are coupled to the common resource and the arbiter. The arbiter control... | 12/16/2003 |
| 6662253 | Shared peripheral architecture A disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor selectably couples each of the plurality of processors to th... | 12/09/2003 |
| 6654833 | Bus arbitration A method for use with a computer system includes permitting a first bus agent to access a bus during predetermined windows of time and preventing a second bus agent from accessing the bus outside of the windows. The first bus agent has a higher priority t... | 11/25/2003 |
| 6651125 | Processing channel subsystem pending I/O work queues based on priorities Asynchronous requests, such as input/output (I/O) requests, within a coprocessor of a computing environment are managed. The management of the asynchronous requests is based on priorities associated with the asynchronous requests. This management includes... | 11/18/2003 |
| 6651119 | Method for allocating priorities to plurality of DMA engines for processing data packets based on bus phase and transactions status A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data... | 11/18/2003 |
| 6651148 | High-speed memory controller for pipelining memory read transactions A memory controller (218) is disclosed which includes a write arbiter (130) and a read arbiter (140) for receiving and processing memory requests from a number of requestor modules (190) for accessing a high speed memory device (110). A high speed control... | 11/18/2003 |
| 6633938 | Independent reset of arbiters and agents to allow for delayed agent reset A system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each agent is provided. The arbiters are reset using a first reset signal, while the agents are rese... | 10/14/2003 |
| 6633939 | Variable-priority arbitration method and respective system A method of arbitration among a plurality of n units which seek access to a resource is regulated according to grants identified by means of an arbitration method, which compares between one another the priorities, generating, for each pair of the units c... | 10/14/2003 |
| 6631433 | Bus arbiter for a data storage system A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second... | 10/07/2003 |
| 6629220 | Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type Dynamic arbitration based on a high priority transaction type. A first memory access request is received at a first request queue. If the first memory access request is of a first type, the priority of the first request queue is dynamically raised over th... | 09/30/2003 |
| 6629177 | Arbitrating requests on computer buses Arbitration requests are received that belong to respective bus types. Each of the types is associated with a programmed value representing a potential number of times that requests of that type may win arbitration events that occur in a given time period... | 09/30/2003 |
| 6622190 | Method for modifying task execution priority in a multitasking, windowed operating environment A method for managing execution priorities in a multitasking operating system. The user sets execution priorities by the position of the application window on the screen relative to the other windows. When the user changes the position of the window, the ... | 09/16/2003 |
| 6618778 | Arbiter for arbitrating between a plurality of requesters and method thereof An arbiter for arbitrating between a plurality of requests from a plurality of requesters, said arbiter being arranged to assign an order of priority of said requesters, the requester having the highest priority and which has made a request winning the ar... | 09/09/2003 |
| 6606691 | System integrating agents having different resource-accessing schemes In a system integrating modules (PROC) designed for a time-slotted resource-accessing scheme and modules (PROC') designed for accessing a common resource based on request-arbitration, a request-arbitration scheme is used for managing access to a common re... | 08/12/2003 |
| 6604160 | Computing system arbitrating and selectively providing resource-seeking tasks with takeaway of non-shareable resources In a computing system with non-shareable resources, use-arbitrating processes are executed on behalf of each task seeking or having access to non-shareable resource. The processes compete according to prescribed rules and priority guidelines, the resoluti... | 08/05/2003 |
| 6594732 | Computer system with memory system in which cache memory is kept clean A computer system includes a host bus, a CPU connected to the host bus, a main memory connected to the host bus, a cache memory and a memory controller. The cache memory is connected to at least one of the host-bus and the CPU, and stores cache data. A ta... | 07/15/2003 |
| 6589187 | Prioritized dynamic memory allocation of arrhythmia episode detail collection A software system implemented in a medical device includes an allocation scheme for allocating storage of cardiac data. The software system enables storing cardiac data in a plurality of addressable locations. When all available locations within the plura... | 07/08/2003 |
| 6591323 | Memory controller with arbitration among several strobe requests A controller for a memory partitioned into a plurality of banks and divided into addresses that are accessed by a plurality of row access strobe signals and a plurality of column access strobe signals. The controller generally comprising a queue state mac... | 07/08/2003 |
| 6587905 | Dynamic data bus allocation A high performance integrated circuit (IC) with independent read and write data busses enables full simultaneous read and write data transfers between devices coupled to the buses. Multiple master and multiple slave devices communicate using the resources... | 07/01/2003 |
| 6587894 | Apparatus for detecting data collision on data bus for out-of-order memory accesses with access execution time based in part on characterization data specific to memory According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed. A data queue coupled to a command queue is arranged to store a time indicating when the data t... | 07/01/2003 |
| 6584532 | Branch searching to prioritize received interrupt signals A data processing system 2 for identifying the highest priority source signal from a plurality of signals each controlling the setting of a bit of a status word held within a status register 10 using programmable mask words. The mask words are used in a b... | 06/24/2003 |
| 6584531 | Arbitration circuit with plural arbitration processors using memory bank history A method and apparatus for arbitrating access to a memory, which has a plurality of banks. The method includes arbitrating with a plurality of processors. Each processor is associated with one of a plurality of data ports and has a plurality of arbitratio... | 06/24/2003 |
| 6557084 | Apparatus and method to improve performance of reads from and writes to shared memory locations According to the present invention, an apparatus and method for improving reads from and writes to shared memory locations is disclosed. By giving writes priority over reads, the current invention can decrease the time associated with certain sequences of... | 04/29/2003 |
| 6542947 | Data bus for serial data transmission A data bus for serial bus transmission between apparatus which are capable of transmitting and/or receiving data via the data bus, recessive and dominant states being present on the data bus and each state being assigned a respective bit value. In order t... | 04/01/2003 |
| 6542944 | Method and apparatus for balancing workloads among paths in a multi-path computer system based on the state of previous I/O operations A method and apparatus for distributing input/output (I/O) operations among at least two paths in a multi-path computer system including a host computer, a system resource and a plurality of paths coupling the host computer to the system resource. For a n... | 04/01/2003 |
| 6539440 | Methods and apparatus for prediction of the time between two consecutive memory accesses According to the present invention, a method for very fast calculation of the earliest command issue time for a new command issued by a memory controller is disclosed. The memory controller includes N page status registers each of which includes four page... | 03/25/2003 |
| 6532510 | Computer system for processing system management interrupt requests A computer system processes system management interrupt (SMI) requests from plural system management (SM) requesters. Different SM requesters are provided with different priority levels such that high priority system management interrupts can be serviced ... | 03/11/2003 |
| 6532505 | Universal resource access controller A universal access controller is described. The universal resource access controller is coupled to a requesting system and a resource, such that when the requesting system desires access to the resource, the requesting system generates a resource access r... | 03/11/2003 |
| 6529935 | Graphics display system with unified memory architecture A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory archite... | 03/04/2003 |
| 6529984 | Dual phase arbitration on a bus A multiphase IEEE 1394 network of nodes requires all nodes to broadcast their current understanding of the phase of the bus (e.g., odd or even). Even if a node is not requesting ownership of the bus, it must send a message that indicates which phase that ... | 03/04/2003 |
| 6510489 | Memory interface circuit A memory bus arbitrating circuit selects the request signal with the highest priority when a plurality of types of same are inputted simultaneously. A memory controlling circuit executes relative to memory control of memory bus arbitrating circuit-selecte... | 01/21/2003 |
| 6510474 | Methods and apparatus for re-reordering command and data packets in order to restore an original order of out-of-order memory requests According to the present invention, techniques for re-reordering command and data packets in order to restore an original order of out-of-order memory requests are described. In one embodiment, a method of increasing data bandwidth by reordering incoming ... | 01/21/2003 |
