Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 5230054 | Priority order judging device Each priority order signal (a code signal having a plurality of digits) is processed at each gate circuit in the following manner. The level of a K-th digit input code signal among the priority order signals is checked and the level of a K-th order judgem... | 07/20/1993 |
| 5202999 | Access request prioritization and summary device An access request prioritization and summary device for determining the current highest priority among n entities. The device includes a bitmap having n bit storage locations. Each one of the n bit storage locations corresponds to one of the entities and ... | 04/13/1993 |
| 5123105 | Priority encoder for a content addressable memory A priority encoder for receiving input request signals at a number of input request terminals and for providing an N-bit output binary code word indicating the binary identification number of the highest-priority, currently-active input request terminal. ... | 06/16/1992 |
| 4939638 | Time sliced vector processing Access by a plurality of instruction streams to a shared resource is managed by preassigning to each instruction stream, arbitration time slots in each of which only one instruction stream is eligible to request access to the resource.... | 07/03/1990 |
| 4926313 | Bifurcated register priority system A dual priority hold register enables the transfer of data to memory ports having serial priority in accordance with two stages of priority. First, all latches of a high priority sector of the register are cleared. Then, the highest priority latch of the ... | 05/15/1990 |
| 4858173 | Apparatus and method for responding to an aborted signal exchange between subsystems in a data processing system In a data processing system in which access to a second unit by a first unit through a system bus is determined by an arbitration unit, when a requesting unit that receives access to the system bus is unable to use that access for interaction with the sec... | 08/15/1989 |
| 4829467 | Memory controller including a priority order determination circuit A resource sharing system including one or more resources, a plurality of resource access devices for accessing the resources, a priority order holder for holding a priority order for access competition between the resources and the resource access device... | 05/09/1989 |
| 4814974 | Programmable memory-based arbitration system for implementing fixed and flexible priority arrangements A digital system has a resource, such as a communication bus, adapted for access by a plurality of devices, a plurality of devices adapted to access the resource, and an arbitrator for arbitrating access to the resource by the devices. The arbitrator incl... | 03/21/1989 |
| 4779089 | Bus arbitration controller A bus arbitration controller controls access of a plurality of asynchronous potential master devices to a unitary interconnecting bus by forming a distributed state machine of arbitration logic units in each of the potential master devices. Each arbitrati... | 10/18/1988 |
| 4774625 | Multiprocessor system with daisy-chained processor selection A multiprocessor system includes a priority discriminator which passes a request signal from a master operation processing unit serially through a plurality of slave operation processing units in accordance with a predetermined priority sequence of the sl... | 09/27/1988 |
| 4722072 | Priority resolution in bus orientated computer systems A priority resolution device for bus orientated computer systems. The system includes a plurality of subsystems, each connected to an associated logic circuit, as well as structure for periodically assigning to each of the subsystems together with input t... | 01/26/1988 |
| 4682282 | Minimum latency tie-breaking arbitration logic circuitry Arbitration apparatus provides first-come-first-served access for a plurality of requestors to a commonly shared unit, such as a memory. Each requestor is provided with a counter which is advanced each cycle from an initial count until its respective requ... | 07/21/1987 |
| 4644467 | Multi-level dynamic priority selector groups of data elements A priority selector includes a plurality of interface circuits (16) each connected to a corresponding data element (13) and operatively connected in common with a priority identification signal generator (15) to selectively interface the data elements (13... | 02/17/1987 |
| 4609995 | Priority controller A priority controller includes a pair of read only memories and a register. The register stores information identifying a request circuit to which priority has recently been granted. Corresponding locations of the two read only memories store identical da... | 09/02/1986 |
| 4604685 | Two stage selection based on time of arrival and predetermined priority in a bus priority resolver A priority resolver for providing unambiguous resolution of requests among competing processes vying for access to a common device and which is adapted to a non-distributed environment.... | 08/05/1986 |
| 4546450 | Priority determination circuit In a priority assignment circuit receiving service request signals and comprising a plurality of service enable signal transmission units for transmitting a service enable signal in accordance with a priority determined by priority signals, bypass circuit... | 10/08/1985 |
| 4493036 | Priority resolver having dynamically adjustable priority levels A data processing system including a dual ported main memory that can be accessed by I/O controllers via a common bus or directly by the central processing unit. The main memory is comprised of a volatile RAM array that requires periodic refreshing to pre... | 01/08/1985 |
| 4481583 | Method for distributing resources in a time-shared system A method is disclosed for distributing processing resources among a plurality of users of a time-shared system wherein resources are divided among various user accounts; each user assigning specific weights to the various programs (processes) in his accou... | 11/06/1984 |
| 4435780 | Separate stack areas for plural processes Multiple processes in an interrupt driven system are efficiently executed because each process has its own independently identified and addressable stack storage area including a process control block. Each process control block includes a link field for ... | 03/06/1984 |
| 4434466 | Apparatus for controlling the access of processors at a data line An apparatus for controlling the access of a plurality of microprocessors at a data line. The microprocessors are connected by interface components or blocks, logic switching circuits and bus drivers with two lines or conductors. An access request or dema... | 02/28/1984 |
| 4348741 | Priority encoder Each channel of a priority encoder register is equipped with a latch for storing one bit of a binary data word. The channel of highest priority generates an output which is applied to encoding means which in turn generates a unique code. The channel outpu... | 09/07/1982 |
| 4339808 | Asynchronous event prioritizing circuit A prioritizing circuit is provided for arbitrating between asynchronously occurring memory access request and memory refresh request signals to a dynamic RAM memory module. The circuit includes a latch circuit (20), a latch control circuit (21), and prior... | 07/13/1982 |
| 4035780 | Priority interrupt logic circuits Priority interrupt apparatus includes a level priority network, a plurality of priority networks, and selector circuits, each corresponding in number to the number of channel sources operative to generate interrupt requests. Each priority network receives... | 07/12/1977 |
| 3947824 | Priority control circuit A priority control circuit for establishing connections between a data handling system element and a number of subsystems wherein request signals from subsystems are scanned and granted service in a sequence which is determined by their position in a prio... | 03/30/1976 |
| 3940745 | Data processing unit having a plurality of hardware circuits for processing data at different priority levels A data processing unit having a plurality of hardware data processing circuits each one including a program counter register for addressing the microinstructions, an accumulator register and an addressing register for storing the addressing of the operand... | 02/24/1976 |
