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| Number | Title | Issue Date |
| 7680971 | Method and apparatus for granting processors access to a resource An apparatus and method for granting one or more requesting entities access to a resource in a predetermined time interval. The apparatus includes a first circuit receiving one or more request signals, and implementing logic for assigning a priority to the one or mo... | 03/16/2010 |
| 7664901 | Data processing apparatus and method for arbitrating access to a shared resource A data processing apparatus and method are providing for arbitrating access to a shared resource. The data processing apparatus has a plurality of logic elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests by one ... | 02/16/2010 |
| 7660928 | Abitration circuit providing stable operation regardless of timing for read and write requests The present invention provides an arbitration circuit capable of stable operation regardless of timings for read and write requests. A latch signal of a predetermined pulse width is generated in accordance with a read request signal or a write request signal and sup... | 02/09/2010 |
| 7657682 | Bus interconnect with flow control A method of operating a bus interconnect coupled to bus masters and bus slaves is provided. The method includes receiving a request from a bus master to perform a bus transaction associated with a transaction ID with a bus slave of the plurality of bus slaves, the b... | 02/02/2010 |
| 7644213 | Resource access manager for controlling access to a limited-access resource Methods and devices utilizing operating system semaphores are described for managing access to limited-access resources by clients. ... | 01/05/2010 |
| 7631132 | Method and apparatus for prioritized transaction queuing A first queue receives transactions from a transaction source in first-in/first-out (FIFO) order regardless of priority. A second queue receives lower priority transactions from the first queue as compared to the higher priority transactions remaining in the first q... | 12/08/2009 |
| 7606957 | Bus system including a bus arbiter for arbitrating access requests A bus system is provided, which includes a shared resource, a shared bus, a plurality of requesters, and a bus arbiter for arbitrating access requests made by the plurality of requesters to access the shared resource through the shared bus. At least one of the plura... | 10/20/2009 |
| 7596647 | Urgency based arbiter An arbiter decides to grant access from multiple clients to a shared resource (e.g. memory) using efficiency and/or urgency terms. Urgency for a client may be determined based on an “in-band” request identifier transmitted from the client to the resource along w... | 09/29/2009 |
| 7574547 | Ring counter based starvation free weighted priority encoded arbiter The embodiments provide an arbiter in a microprocessor that can handle requests to access a shared resource from function units with different priorities without starving the access opportunities of requests from function units with low priority. In one embodiment, ... | 08/11/2009 |
| 7529874 | Semiconductor integrated circuit device for real-time processing A technology capable of efficiently performing the processes by using limited resources in an LSI where a plurality of real-time applications are parallelly processed is provided. To provide such a technology, a mechanism is provided in which a plurality of processe... | 05/05/2009 |
| 7500038 | Resource management A resource management system including a plurality of requester elements competing to access a resource through an arbiter element that controls access to the resource by the requester elements. A requester element having a buffer unit and first and second counters,... | 03/03/2009 |
| 7441087 | System, apparatus and method for issuing predictions from an inventory to access a memory A system, apparatus, and method are disclosed for managing predictive accesses to memory. In one embodiment, an exemplary apparatus is configured as a prediction inventory that stores predictions in a number of queues. Each queue is configured to maintain prediction... | 10/21/2008 |
| 7426600 | Bus switch circuit and bus switch system A bus switch circuit having plural master side interface circuits inputting/outputting signals for plural bus masters respectively, and one or plural slave side interface circuit(s) inputting/outputting signals for one or plural bus slave(s), is provided. The master... | 09/16/2008 |
| 7426594 | Apparatus, system, and method for arbitrating between memory requests Apparatus, system, and method for arbitrating between memory requests are described. In one embodiment, a processing apparatus includes a memory request generator configured to generate memory requests specifying data for respective presentation elements. The memory... | 09/16/2008 |
| 7426603 | Memory bus arbitration using memory bank readiness A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapa... | 09/16/2008 |
| 7426560 | Method and system for managing quality of service in a network According to embodiments, the present invention comprises a method and system for managing support of quality of service requirements for various clients of a telecommunications network at a server level. Servers assigned to the various clients may include quality o... | 09/16/2008 |
| 7421521 | System, method and device for real time control of processor A method and device of synchronizing interrupts of a processor with, for example, signals from a synchronization unit such as, for example, a slot timer. In advance of the start of a slot as may, for example, be indicated by a signal from, for example, a slot timer,... | 09/02/2008 |
| 7415556 | Exclusion control An exclusion controller which allows an information processing unit to acquire a contended resource to the exclusion of the other information processing units includes a plurality of non-prioritized information processing units mutually exclusively acquiring a non-p... | 08/19/2008 |
| 7406690 | Flow lookahead in an ordered semaphore management subsystem In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the... | 07/29/2008 |
| 7404024 | Method for arbitrating access to a shared resource A method for arbitrating access to a resource shared by several electronic elements. Each element is allocated a first counting value and a first penalty, the first counting value is decremented in synchronization with a clock signal, and is incremented by a value e... | 07/22/2008 |
| 7404025 | Software programmable dynamically reconfigurable scheme for controlling request grant and masking for ultra high priority accessor during arbitration A method for arbitration grants access to an ultra high priority device if the ultra high priority device requests access. This access is limited to a selectable number of accesses. Thereafter the ultra high priority device is masked from requesting access for a sel... | 07/22/2008 |
| 7395360 | Programmable chip bus arbitration logic Methods and apparatus are provided for implementing a bus arbitration priority encoding scheme with fairness. Bus arbitration logic is connected to multiple primary components or devices. The multiple primary components send requests to bus arbitration logic. The bu... | 07/01/2008 |
| 7392353 | Prioritization of out-of-order data transfers on shared data bus Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers ... | 06/24/2008 |
| 7386645 | System on a chip with an arbitration unit to grant right of access to a common resource in response to conflicting requests for access from initiator modules, and storage key incorporating the arbitration unit An electronic system comprises a defined number N of functional modules, including a defined number P of initiator modules and a defined number Q of target modules, where N, P and Q are integer numbers such that 2≦P≦N and 1≦Q≦N. In the event of a plurality o... | 06/10/2008 |
| 7380040 | Software programmable dynamic arbitration scheme A method for arbitration among a plurality of requesting devices for a shared resource in which one device is an ultra high priority device grants access to one requesting device at a time. The ultra high priority device is granted access if it requests access inter... | 05/27/2008 |
| 7380039 | Apparatus, method and system for aggregrating computing resources A system for executing applications designed to run on a single SMP computer on an easily scalable network of computers, while providing each application with computing resources, including processing power, memory and others that exceed the resources available on a... | 05/27/2008 |
| 7373438 | System and method for reprioritizing high-latency input/output operations A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by including a hurry up command that adjusts the latency of a given input/... | 05/13/2008 |
| 7373445 | Method and apparatus for allocating bus access rights in multimaster bus systems A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device is assigned a priority value from an organized priority list of priority values. Requests from at least ... | 05/13/2008 |
| 7373448 | Method, system, and program for building a queue to test a device Provided are a method, system, and device for signaling a reconnection inhibitor over a bus to cause the reconnection inhibitor to access the bus to inhibit an Input/Output (I/O) controller from accessing the bus. An initiator transmits I/O requests on the bus to th... | 05/13/2008 |
| 7373522 | Smart card with enhanced security features and related system, integrated circuit, and methods An integrated circuit (IC) may include at least one smart card memory for storing a set of default requests and at least one alternate request for each default request. The IC may further include a microprocessor connected to the at least one smart card memory for c... | 05/13/2008 |
| 7370161 | Bank arbiter system which grants access based on the count of access requests Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and al... | 05/06/2008 |
| 7369982 | Multi-mode smart card emulator and related methods An emulator for a multi-mode smart card may include emulation circuitry for performing smart card applications in a plurality of operational modes. The emulator may also include a smart card connector to be connected to a smart card adapter operable in at least one ... | 05/06/2008 |
| 7365757 | Method and apparatus for independent video and graphics scaling in a video graphics system A method and apparatus for independent video and graphics scaling in a video graphics system is accomplished by receiving a video data stream, wherein the video data stream includes video data in a first format. A graphics data stream is also received, and the graph... | 04/29/2008 |
| 7366810 | Method and system for multi-processor arbitration A computing system includes one or more buses, a plurality of bus agents, and a chip set. The plurality of bus agents are capable of accessing at least one of the buses. The chipset arbitrates access to a bus for at least two of the bus agents such that utilization ... | 04/29/2008 |
| 7366812 | Determination of access rights to information technology resources A method, system, and firewall for controlling access to resources within an information technology (IT) system. Commands received from a requesting entity request access to a resource associated with each command. An assigned authority level of the requesting entit... | 04/29/2008 |
| 7363406 | Dynamic access scheduling memory controller Bus transactions in a memory controller are scheduled by storing a set of configuration parameters that define a bus scheduling policy, generating values of a set of dynamic cost functions for each bus transaction, ordering the bus transactions in accordance with th... | 04/22/2008 |
| 7356043 | Network channel access protocol—slot scheduling Network channel access protocol is disclosed. More particularly, a distributed, locally determined, channel access protocol that adapts to load, avoids interference and controls access by a group of nodes to a set of shared channels is disclosed. Shared channel spac... | 04/08/2008 |
| 7353311 | Method of accessing information and system therefor A method is disclosed whereby a priority amongst transactions capable of being processed at a common time is determined based upon a transaction identifier associated with each of the transaction. The transaction identifier can either directly indicate a priority am... | 04/01/2008 |
| 7353362 | Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means con... | 04/01/2008 |
| 7350004 | Resource management device Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessin... | 03/25/2008 |