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| Number | Title | Issue Date |
| 7054971 | Interface between a host and a slave device having a latency greater than the latency of the host An interface between a host and a slave device having a latency greater than the latency of the host is disclosed. The interface includes a register and a state machine. The state machine provides data to the host from any address in the slave in two host read cycle... | 05/30/2006 |
| 7054966 | Data processing system A data processing system in accordance with an exemplary embodiment is provided. The data processing system includes a first host device operably coupled to a first PCI communication bus wherein the first host device substantially only performs tasks associated with... | 05/30/2006 |
| 7054968 | Method and apparatus for multi-port memory controller A memory controller is provided. The memory controller includes an initiator block configured to arbitrate requests corresponding to data from multiple ports. The initiator block includes an arbitration module configured to consider a latency factor and a bandwidth ... | 05/30/2006 |
| 7051133 | Arbitration circuit and data processing system An arbitration circuit and a data processing system which ensure fair bus access are provided. An arbitration circuit (1) has a priority check block (21) and a round robin block (22). The priority check block (21) checks pieces of priorit... | 05/23/2006 |
| 7051172 | Memory arbiter with intelligent page gathering logic Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The ar... | 05/23/2006 |
| 7051073 | Method, system and program for efficiently distributing serial electronic publications A data processing system with efficient facilities for transmitting a serial electronic publication to subscribers includes a push engine and a status manager. The push engine transmits a first issue to a subscriber. The status manager determines whether the first i... | 05/23/2006 |
| 7051132 | Bus system and path decision method therefor A bus system and a method of deciding a data transmission path are provided. The bus system includes a plurality of functional blocks; a ring bus which transmits data in a single direction; an arbiter which generates a bus grant signal according to a predetermined a... | 05/23/2006 |
| 7050453 | Method and apparatus for ensuring compatibility on a high performance serial bus A data communications system is disclosed having at least one Legacy cloud coupled to at least one Beta cloud. The system further having at least one BOSS node and at least one border node. A method for ensuring compatibility is disclosed comprising determining when... | 05/23/2006 |
| 7047337 | Concurrent access of shared resources utilizing tracking of request reception and completion order An apparatus, program product and method to manage access to a shared resource by a plurality of processes in a multithreaded computer via a collection of atomic operations that track both the order in which requests that use a shared resource are received, and the ... | 05/16/2006 |
| 7047468 | Method and apparatus for low overhead circuit scan A method and system for manipulating data in a state holding elements array. Process data is moved through the state holding elements array by a process controller. A separate scan controller scans data out of the state holding elements array by scanning data out of... | 05/16/2006 |
| 7043542 | Information processing method and system for reserving and information processing apparatus having globally unique identification information In the case where a reservation has been made via a bridge in, e.g., an IEEE 1394 serial data bus, and bus resetting has occurred in a bus connected to the reserve owner, it is desirable that another bus connected to the bridge is able to find the reserve owner. To ... | 05/09/2006 |
| 7043581 | Resource sequester mechanism A method and system for controlling access to selected resources in a computer system. The system includes a processor and a device coupled to the processor. The device includes one or more sub-devices and one or more access locks. The access locks are configured to... | 05/09/2006 |
| 7039061 | Methods and apparatus for retaining packet order in systems utilizing multiple transmit queues Methods, apparatus, and articles of manufacture for retaining packet order in multiprocessor systems utilizing multiple transmit queues are disclosed herein. Embodiments of the present invention define multiple transmit queues for a given priority level of packets t... | 05/02/2006 |
| 7039690 | System and method for accessing registers of PHY device in network A system and method for accessing registers of a PHY device in a network including an extended protocol software layer between the protocol and application layers, on the one hand, and the MAC driver, on the other hand. The extended protocol layer generates the PHY ... | 05/02/2006 |
| 7039916 | Data delivery system for adjusting assignment of connection requests to nodes based upon the tracked duration The time taken for connection establishment is monitored to aid in selecting load distribution among nodes in a data delivery system, such as a server cluster. The failure of a node to respond to a connection request may be used to identify a crashed node. The numbe... | 05/02/2006 |
| 7039736 | Systems and methods for accessing bus-mastered system resources Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbi... | 05/02/2006 |
| 7039737 | Method and apparatus for resource arbitration A method and apparatus is described for controlling accesses to a shared resource. An arbitration mechanism uses a register, accessible by each device sharing the resource. The register may be written by the device to request access to the resource, and read by the ... | 05/02/2006 |
| 7035981 | Asynchronous input/output cache having reduced latency The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device in... | 04/25/2006 |
| 7035958 | Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target A method of operating a request FIFO of a system on a chip (SoC) in which a requests in a first position that has been granted and which subsequently receives a retry from the intended target is automatically re-ordered with respect to the other requests below it in... | 04/25/2006 |
| 7035963 | Method for resolving address space conflicts between a virtual machine monitor and a guest operating system In one embodiment, a method for resolving address space conflicts includes detecting that a guest operating system attempts to access a region occupied by a first portion of a virtual machine monitor and relocating the first portion of the virtual machine monitor wi... | 04/25/2006 |
| 7032048 | Method, system, and program products for distributed content throttling in a computing environment A method (and structure) in a computer network of controlling the admittance of requests to at least one processing component, includes differentiating the type of received requests based on the message content in each request. Each request is admitted only if the d... | 04/18/2006 |
| 7028121 | Parameter generating circuit for deciding priority of master blocks and method of generating parameter Provided are a parameter generating circuit and a method of generating a parameter which decides priority of master blocks. An arbitration parameter generating circuit includes a counter, a short term arbitration parameter storage unit, a short term reference time m... | 04/11/2006 |
| 7028120 | Apparatus and method for reducing LDRQ input pin count of a low pin count host using serially coupled peripheral devices An apparatus and method for reducing LDRQ input pin count of a low pin count (LPC) host are provided. The LPC host is series of connecting with a plurality of peripheral devices, the peripheral device having a LDRQ control device within. The LDRQ control device comp... | 04/11/2006 |
| 7028115 | Source triggered transaction blocking A system may include at least a first agent and a second agent, and the first agent may be coupled to receive a block signal generated by the second agent. The block signal is indicative of whether or not the second agent is capable of participating in transactions.... | 04/11/2006 |
| 7028118 | Multi-channel buffered serial port debugging In digital signal processors serial data is passed in out and of the chip in a time division multiplexed (TDM) fashion. The TDM stream consists of many independent channels of serial data. The complexity of generating interleaved TDM serial data from multiple source... | 04/11/2006 |
| 7028106 | Remapping routing information entries in an expander A system includes a peripheral device and an expander having interfaces to couple to one or more peripheral devices and an expander. The expander has a storage to store entries containing routing information used to route a request received by the expander to one of... | 04/11/2006 |
| 7023874 | Distributed arbitration on a full duplex bus Distributed arbitration in a full-duplex bus system. By distributing the arbitration function among the nodes of a tree topology full-duplex bus system such that arbitration at any particular time is handled by a node holding a grant of the bus at that time (the nom... | 04/04/2006 |
| 7024432 | Updating computer files on wireless data processing devices A wireless data processing device 2 stores partially completed versions of a file needed to replace a current version of a file used by that target device 2. When a device storing a more up-to-date version of the file than the current complete version ... | 04/04/2006 |
| 7024503 | Link bus between control chipsets and arbitration method thereof A bus structure is implemented within a control chipset between a first control chip and a second control chip, comprising a first AD bus and a second AD bus. According to an arbitration method implemented to allow a dynamic adjustment of the direction of the AD bus... | 04/04/2006 |
| 7024506 | Hierarchically expandable fair arbiter A plurality of arbitration devices is hierarchically coupled and has a plurality of child devices and at least one parent device. Each of the plurality of arbitration devices is operable to store a previous arbitration winner. In addition, the plurality of arbitrati... | 04/04/2006 |
| 7020807 | Data communication bus traffic generator arrangement A circuit arrangement including a test-traffic generator, and adapted to communicate test-traffic onto a digital data path having other traffic sources. A first embodiment includes a data-generation circuit, a memory arrangement, state machine circuitry, and a statu... | 03/28/2006 |
| 7020733 | Data bus system and method for performing cross-access between buses A data bus system, capable of distributing devices including first and second data buses capable of transmitting data among a plurality of devices; a register block that stores information on a first bus request signal and a first bus grant signal; a global arbiter ... | 03/28/2006 |
| 7016995 | Systems and methods for preventing disruption of one or more system buses A system prevents disruption of one or more system buses. The system monitors communication on the one or more system buses during an input mode and an output mode and detects changes between the input mode and the output mode. The system determines whether a predet... | 03/21/2006 |
| 7017018 | Method and apparatus for a virtual memory file system Methods and a system for a RAM based file system are provided. One exemplary system provides a RAM file system integrated into a host adapter card that connects to a host computer that has access to a storage device. The host adapter card includes a bus interface an... | 03/21/2006 |
| 7012930 | Apparatus and method for pre-arbitrating use of a communication link A method of reserving access to a shared communication link by a number of devices is disclosed, having the steps of: (1) assigning a plurality, m, of counters to each of the number of devices, each counter counting from a first count value to a second count value; ... | 03/14/2006 |
| 7013339 | Method to control a network device in a network comprising several devices A method to control a network device in a network comprising several devices includes a first controller that operates to prevent another controller from performing an unwanted overtaking of a network device that is currently controlled by the first controller. In o... | 03/14/2006 |
| 7013357 | Arbiter having programmable arbitration points for undefined length burst accesses and method An arbitration control circuit (11) for arbitrating access to a slave device (4) by a plurality of master devices (2, 3) includes an undefined length burst (ULB) arbitration logic circuit (12). The ULB arbitration logic circuit (12... | 03/14/2006 |
| 7012914 | Methods and apparatus for fibre channel interconnection of private loop devices Methods and apparatus for Fibre Channel interconnection is provided between a plurality of private loop devices through a Fibre Channel private loop device interconnect system. In the preferred embodiments, the Fibre Channel private loop device interconnect system i... | 03/14/2006 |
| 7007122 | Method for pre-emptive arbitration An interface system capable of providing pre-emptive arbitration among multiple agents comprises an interface including at least a first agent and a second agent which share the interface for transferring data, the second agent having priority over the first agent f... | 02/28/2006 |
| 7007123 | Binary tree arbitration system and method using embedded logic structure for controlling flag direction in multi-level arbiter node A binary-tree-based arbitration system and methodology with attributes that approximate a Generalized Processor Sharing (GPS) scheme for rendering fairer service grants in an environment having a plurality of competing entities. Arbitration based on probabilistic co... | 02/28/2006 |
