Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 4845624 | Relational data base lock avoidance system The present invention is directed to a relational data base system which is operating in a virtual machine environment. The invention provides a system that includes a disconnected virtual machine which is running in the same virtual machine environment a... | 07/04/1989 |
| 4835677 | System for directly and indirectly accessing control registers by different operating systems based upon value of operating system indication bit A data processing system comprising at least two operating systems (OS1, OS2) for virtual machines, a supervisory operating system, i.e., a control program (CP) for controlling the operating systems, control registers (CR0, CR1, ---) and an extended contr... | 05/30/1989 |
| 4821177 | Apparatus for controlling system accesses having multiple command level conditional rotational multiple port servicing priority hierarchy The apparatus controls access to at least one subsystem in response to requests for access from a plurality of equipments operatively connected to a corresponding port of said apparatus. The requests for access have a plurality of command levels wherein t... | 04/11/1989 |
| 4787032 | Priority arbitration circuit for processor access A personal computer is disclosed having a microprocessor RESET/HOLD arbitration circuit and logic. The RESET/HOLD arbitration circuit requires a RESET signal to wait until any pending microprocessor "HOLD" is serviced or in the alternative and in the even... | 11/22/1988 |
| 4772888 | Bus state control circuit A bus state control circuit controls the access operation on the basis of access request signals supplied thereto. The access of an input-output device starts after a predetermined time interval in the case when a previous access was made to the input-out... | 09/20/1988 |
| 4773037 | Increased bandwidth for multi-processor access of a common resource This circuitry permits equal access to a shared resource by a number of central processing units (CPUs). In a multiple CPU arrangement, common resource contention problems arise, when several CPUs attempt to access the common resource. To resolve these co... | 09/20/1988 |
| 4739324 | Method for serial peripheral interface (SPI) in a serial data bus In a communication system for the transmission of messages through a data bus between one or more user microprocessors coupled to the data bus, the user microprocessors having either a serial communications interface (SCI) port or a serial peripheral inte... | 04/19/1988 |
| 4734881 | Microprocessor controlled signal discrimination circuitry Circuitry for the validation of repetitive signals including input/output circuitry providing information regarding signals received that is connected to a progammable microprocessor, a read only memory and random access memory. The microprocessor is prog... | 03/29/1988 |
| 4719458 | Method of data arbitration and collision detection in a data bus A method of blocking data transmission from a user microprocessor to a data bus utilizing arbitration and collision detection in a data bus interface integrated circuit utilizing a Serial Communication Interface (SCI) port on the user microprocessor.... | 01/12/1988 |
| 4706082 | Serial data bus for intermodule data communications A bus interface integrated circuit is presented which utilizes an arbitration detector, a collision detector and a contention permitting differential transceiver to work with a serial communication interface port on a microprocessor to determine between c... | 11/10/1987 |
| 4667192 | Method and apparatus for bus arbitration using a pseudo-random sequence The present invention discloses a second level bus arbitration method and apparatus for use with a distributed computer network. The invention alleviates any simultaneous access possibility by requiring any computing element which claims access to the bus... | 05/19/1987 |
| 4652873 | Access control for a plurality of modules to a common bus A priority system for controlling the sequence in which requests made by modules, connected in parallel to a common bus, for access to the common bus is granted. A bus busy line is maintained at a first predetermined voltage if the common bus is not busy,... | 03/24/1987 |
| 4642630 | Method and apparatus for bus contention resolution A method and apparatus for bus contention resolution for use in a digital communications system wherein a plurality of communications controllers are connected to a shared bus for transmitting information in frames. A priority field is included in each tr... | 02/10/1987 |
| 4633394 | Distributed arbitration for multiple processors A method of arbitrating for N processors requesting access to a shared resource utilizing 2 log2 N shared variables, such as electrical lines. Each processor can assert a line which is asserted if any processor is asserting it. A requesting pro... | 12/30/1986 |
| 4631534 | Distributed packet switching system A distributed packet switching system in which a centralized switch is not used and, instead, each transmitting port contains the intelligence required to derive and then insert the destination port and station addresses into the header of each packet to ... | 12/23/1986 |
| 4626843 | Multi-master communication bus system with parallel bus request arbitration Apparatus and a related method for regulating access to a communication bus to which multiple communication nodes are connected. Control logic at each of the nodes determines which of them has priority to access the bus, by means of a parallel arbitration... | 12/02/1986 |
| 4627018 | Priority requestor accelerator A system for accelerating the granting of prioritized memory requests to a multi port memory system of a data processing system is disclosed. The priority requestor accelerator system detects the fact that one remaining requestor is in the priority memory... | 12/02/1986 |
| 4612542 | Apparatus for arbitrating between a plurality of requestor elements An arbitration circuit comprises a plurality of enabling elements which determines when predetermined conditions exist to transmit a request signal. A first gate combines transmitted request signals to generate a combined request signal. A plurality of fi... | 09/16/1986 |
| 4354227 | Fixed resource allocation method and apparatus for multiprocessor systems having complementarily phased cycles In multiprocessor data processing systems that utilize individual processors having interlaced cycles of operation controlled by complementarily phased clocks, contention for fixed resources such as memory, I/O, or data storage for example, may result unl... | 10/12/1982 |
| 4318182 | Deadlock detection and prevention mechanism for a computer system A method and apparatus for detecting a deadlock condition where two or more processes are waiting for events which cannot happen. Firmware is provided to examine the request of a first process of a group of processes for assignment of a first resource of ... | 03/02/1982 |
| 4191997 | Circuits and methods for multiple control in data processing systems In a data processing system in which two or more asynchronous processors operating as masters interchange requests and responses with a control unit that in turn controls a number of peripheral devices and operates as a slave to the processors, repetitive... | 03/04/1980 |
| 4016539 | Asynchronous arbiter An asynchronous arbiter for use in systems where two or more signal sources attempt to simultaneously use a resource operates to insure that signal source requests are honored in the sequence of the earliest generated request to the latest generated reque... | 04/05/1977 |
