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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 7529873 | Determination of access rights to information technology resources A system and firewall for controlling access to resources within an information technology system. Commands received from a requesting entity request access to a resource associated with each command. An assigned authority level of the requesting entity is identifie... | 05/05/2009 |
| 7516259 | Combined engine for video and graphics processing The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritizati... | 04/07/2009 |
| 7506090 | System and method for user-configurable resource arbitration in a process control system A system includes at least one memory and at least one processor. The at least one memory is operable to store a resource object associated with a resource. The at least one memory is also operable to store a plurality of requester objects associated with at least a... | 03/17/2009 |
| 7496705 | Method and computer readable medium for suspended state resource adapter In accordance with embodiments, there are provided mechanisms and methods for suspending work by a resource adapter. These mechanisms and methods for suspending work by a resource adapter can enable embodiments to provide the capability to start and stop work perfor... | 02/24/2009 |
| 7478184 | Integrated circuit device including processor selection in a multiprocessor system An integrated circuit device in which a CPU not to be used of a plurality of CPUs formed on one chip can easily be disconnected by an external signal in order to reduce the costs of developing an LSI. In accordance with a CPU selection signal inputted from the outsi... | 01/13/2009 |
| 7469309 | Peer-to-peer data transfer method and apparatus with request limits Methods and apparatus for peer-to-peer data transfers in a computing environment provide configurable control over the number of outstanding read requests by one peer device to another. A requesting peer device includes a control register that stores a high-watermar... | 12/23/2008 |
| 7467247 | Timeouts on accessing a shared resource A computer-implemented method of generating timeout errors based on shared register access by two processors is described. A processor access timer is started responsive to generation of an access request by a first processor. The generated first processor access re... | 12/16/2008 |
| 7444668 | Method and apparatus for determining access permission A method and apparatus for determining access protection (96) includes receiving a plurality of access requests (84) corresponding to a plurality of masters (12, 14), determining access permissions (86), providing state information (60... | 10/28/2008 |
| 7441059 | Method and device for data communication A device for data communication between a first host device or a further host device and at least one client device along a shared transmission path includes a first host device, which includes a host application; at least one further host device, which includes a h... | 10/21/2008 |
| 7437495 | Method and apparatus for assigning bus grant requests Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an... | 10/14/2008 |
| 7437493 | Modular architecture for a network storage controller A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be... | 10/14/2008 |
| 7428609 | Method and system to partition hardware resources between operating systems Disclosed is a method and system to partition hardware resources between operating systems. A determination is made whether a first PCI resource attached to a line of a bus is to be sequestered to a service operating system (OS). If so, the first PCI resource is seq... | 09/23/2008 |
| 7426603 | Memory bus arbitration using memory bank readiness A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapa... | 09/16/2008 |
| 7426607 | Memory system and method of operating memory system A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of memory devices. The memory bus is configured to alternatively couple the m... | 09/16/2008 |
| 7426735 | Threading and communication architecture for a graphical user interface A system and method to facilitate communication between a user interface and an associated process is disclosed. A first thread is associated with the user interface and a second thread is associated with the process for implementing requests by the user interface. ... | 09/16/2008 |
| 7421693 | Logic for synchronizing multiple tasks at multiple locations in an instruction stream Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”... | 09/02/2008 |
| 7418535 | Bus system and method of arbitrating the same A bus system, which may prevent data from being incorrectly transferred when an early termination occurs during a burst mode, may include a bus, for example, an advanced high-performance bus (AHB), at least one bus master device, a bus arbiter and at least one trans... | 08/26/2008 |
| 7417637 | Fairly arbitrating between clients An apparatus and method for fairly arbitrating between clients with varying workloads. The clients are configured in a pipeline for processing graphics data. An arbitration unit selects requests from each of the clients to access a shared resource. Each client provi... | 08/26/2008 |
| 7418561 | Adaptive throttling of memory accesses, such as throttling RDRAM accesses in a real-time system Apparatus and methods to adaptively throttle accesses to memory employ a masking tool to specify the percentage of memory bandwidth available for access. The apparatus applies the mask and monitors the number of memory accesses during a throttle-monitoring window. I... | 08/26/2008 |
| 7412550 | Bus system with protocol conversion for arbitrating bus occupation and method thereof A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus control is transferred to another one of the plurality of masters, thereb... | 08/12/2008 |
| 7412513 | Systems and methods for using metrics to control throttling and swapping in a message processing system A system and method of using metrics to control throttling and swapping in a message processing system is provided. A workload status of a message processing system is determined, and the system polls for a new message according to the workload status. The message p... | 08/12/2008 |
| 7408950 | Multiple node network and communication method within the network A multiple node network includes a plurality of terminal nodes. A management node manages the terminal nodes. A bus connects the respective terminal nodes and the management node to one another. The respective terminal nodes and the management node communicate with ... | 08/05/2008 |
| 7406690 | Flow lookahead in an ordered semaphore management subsystem In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the... | 07/29/2008 |
| 7404024 | Method for arbitrating access to a shared resource A method for arbitrating access to a resource shared by several electronic elements. Each element is allocated a first counting value and a first penalty, the first counting value is decremented in synchronization with a clock signal, and is incremented by a value e... | 07/22/2008 |
| 7404023 | Method and apparatus for providing channel bonding and clock correction arbitration A method and apparatus for providing channel bonding and clock correction arbitration in integrated circuits are disclosed. An arbitration device analyzes indicators to determine when clock correction request or a channel bonding request occur simultaneously. Then, ... | 07/22/2008 |
| 7398343 | Interrupt processing system An interrupt processing system having an interrupt holding registers, each corresponding to a different class of interrupts. A write queue posts servicing required by the interrupt holding registers. An interrupt vector register has bit positions corresponding to di... | 07/08/2008 |
| 7392335 | Anticipatory changes to resources managed by locks A method and system are provided for performing anticipatory changes to a resource governed by a locking mechanism. Entities (such as transactions in a database system) that want to modify a resource request permission to modify the resource. However, prior to recei... | 06/24/2008 |
| 7386639 | Switch for coupling one bus to another bus A communication module includes a switch circuit operable to connect an internal bus to an external bus for, e.g., diagnostics, verification, and fault analysis. The internal bus allows data communication between electronic components internal to the communication m... | 06/10/2008 |
| 7383395 | Storage device A storage system is disclosed for performing control to match data among cache memories corresponding to shared volumes when multiple disk controllers containing cache memories are accessing shared volumes formed in the storage device. The storage system contains a ... | 06/03/2008 |
| 7380038 | Priority registers for biasing access to shared resources A priority register is provided for each of a multiple processor cores of a chip multiprocessor, where the priority register stores values that are used to bias resources available to the multiple processor cores. Even though such multiple processor cores have their... | 05/27/2008 |
| 7380036 | Combined engine for video and graphics processing The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritizati... | 05/27/2008 |
| 7373453 | Method and apparatus of interleaving memory bank in multi-layer bus system A method and apparatus of interleaving memory banks in a multi-layer bus system. The apparatus includes a plurality of slave interface units receiving signals requesting a bus access and generating control signals, and a controller receiving the control signals gene... | 05/13/2008 |
| 7373438 | System and method for reprioritizing high-latency input/output operations A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by including a hurry up command that adjusts the latency of a given input/... | 05/13/2008 |
| 7373445 | Method and apparatus for allocating bus access rights in multimaster bus systems A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device is assigned a priority value from an organized priority list of priority values. Requests from at least ... | 05/13/2008 |
| 7370131 | High-speed data readable information processing device A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal.... | 05/06/2008 |
| 7370161 | Bank arbiter system which grants access based on the count of access requests Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and al... | 05/06/2008 |
| 7369380 | Highly available dual serial bus architecture In a highly available storage system, an enclosure includes first and second power supplies, and first and second controller boards. Each of the first and second controller boards includes first and second serial bus controllers. First and second serial buses are co... | 05/06/2008 |
| 7366968 | Data processing apparatus, and its processing method, program product and mobile telephone apparatus A data processing apparatus capable of preventing contention of memory access between the HARQ synthesis and rate dematching in the HARQ processing using two or more single-port memories is provided. A buffer includes two physical memories. One of the physical memor... | 04/29/2008 |
| 7366810 | Method and system for multi-processor arbitration A computing system includes one or more buses, a plurality of bus agents, and a chip set. The plurality of bus agents are capable of accessing at least one of the buses. The chipset arbitrates access to a bus for at least two of the bus agents such that utilization ... | 04/29/2008 |
| 7366812 | Determination of access rights to information technology resources A method, system, and firewall for controlling access to resources within an information technology (IT) system. Commands received from a requesting entity request access to a resource associated with each command. An assigned authority level of the requesting entit... | 04/29/2008 |
