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| Number | Title | Issue Date |
| 6950884 | Device and method for bidirectional data transfer between two processors wherein DMA channel provides improved data transfer between processors A device for the bidirectional transfer of data between two processors contains input and output control information memories for storing an item of binary control information for input and output memories. The memories can be accessed by the second processor and, v... | 09/27/2005 |
| 6948024 | Expander device for isolating bus segments in I/O subsystem An expander device and method for isolating bus segments from one another in an I/O subsystem. The expander device is arranged to couple the bus segments for communication in the I/O subsystem. The expander device includes a first I/O interface circuit, a second I/O... | 09/20/2005 |
| 6948030 | FIFO memory system and method A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and... | 09/20/2005 |
| 6948019 | Apparatus for arbitrating non-queued split master devices on a data bus A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An input gate is responsive to the status of the slave device and to receipt... | 09/20/2005 |
| 6948036 | System and method for providing multi-initiator capability to an ATA drive A multi-port adapter and method of operation suitable for use with serial ATA devices is disclosed. An adapter includes a switch that receives input from multiple host devices and an arbiter module for assigning a priority scheme to received commands. An outstanding... | 09/20/2005 |
| 6942157 | Data processing system and data processing method An IC chip is provided with a wireless unit for inputting and outputting data by wireless communication, in addition to a logic section, so that the IC chip no longer needs I/O pads, leaving only power supply and ground pads. IC chips can input and output data with ... | 09/13/2005 |
| 6944705 | Method and apparatus for automatic detection and healing of signal pair crossover on a high performance serial bus An automatic crossover and healing process is disclosed for the P1394b standard. In particular, a crossover process is disclosed which comprises coupling the transmitting logic of a PHY to TPA, and coupling the receive logic of a PHY to TPB. ... | 09/13/2005 |
| 6941409 | Switching and connecting arrangement for coupling external and internal antennas with an expansion card A switching and connecting arrangement for coupling external and internal antennas, wherein the arrangement comprises at least a diversity switch arranged on a circuit board for selecting a first antenna or a second antenna. The arrangement also comprises a first in... | 09/06/2005 |
| 6938130 | Method and apparatus for delaying interfering accesses from other threads during transactional program execution One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another t... | 08/30/2005 |
| 6934775 | Operating method for a data bus for several users with flexible timed access The invention relates to an operating method for a data bus for several parties with flexible, timed access. According to the method, the parties are synchronized, the bus messages are sent from the parties in a hierarchical sequence and are sent at least in part, o... | 08/23/2005 |
| 6934782 | Process and apparatus for managing use of a peripheral bus among a plurality of controllers Ownership of a peripheral bus between a peripheral device and a plurality of master devices is assigned to one of the master devices. Each master device has an associated controller for controlling the peripheral device via the peripheral bus. Communication occurs w... | 08/23/2005 |
| 6934784 | Systems and methods for managing-system-management-event data A method and system for system-management event detection, consolidation, reporting and storage is provided. The method and system may be used in a computer system for above-mentioned purposes. The method and system may be connected to central processing unit throug... | 08/23/2005 |
| 6934951 | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing... | 08/23/2005 |
| 6931471 | Method, apparatus, and computer program product for migrating data subject to access by input/output devices A computer system has physical pages of memory subject to access by input/output (“I/O”) devices, and a certain table with entries associating the physical pages with the I/O devices. Responsive to a request for data be moved from a first physical page to a seco... | 08/16/2005 |
| 6928500 | High speed bus system that incorporates uni-directional point-to-point buses A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a centr... | 08/09/2005 |
| 6928523 | Synchronous signal producing circuit for controlling a data ready signal indicative of end of access to a shared memory and thereby controlling synchronization between processor and coprocessor A synchronous signal producing circuit includes an access inhibit region register for designating an access inhibit region for a processor in a shared memory, a comparing circuit for detecting the access by the processor to the access inhibit region designated in th... | 08/09/2005 |
| 6925556 | Method and system to determine the bootstrap processor from a plurality of operable processors Methods, apparatuses, and systems are provided to determine a bootstrap processor. In an embodiment, the method determines a bootstrap processor from a plurality of operable processors in a fault tolerant multiprocessor system irrespective of an initialization time ... | 08/02/2005 |
| 6917996 | Bus control system and method of controlling bus An external bus control device 2 has first and second bus controllers 15, 16 and an external bus arbiter 17. The bus controllers 15, 16 correspond to devices (for example, SRAM, DRAM) connected to an external bus EXBUS respectively. The b... | 07/12/2005 |
| 6915354 | Distributed iSCSI and SCSI targets Apparatus and methods for distributing iSCSI and SCSI targets. The initiator may assist in the distribution and order the SCSI commands. A subset of target storage processors may act as proxies. Target storage processors forward requests to a selected target storage... | 07/05/2005 |
| 6915522 | System and method to synchronize two or more object management systems A distributed reader and writer's lock to synchronize object management systems is disclosed. The purpose of the lock is to control access to information that is shared by corresponding object management system components on multiple object management systems. An ob... | 07/05/2005 |
| 6912610 | Hardware assisted firmware task scheduling and management A data processing module having a central processing unit and a task management control method and apparatus is disclosed which may comprise: a plurality of task identifiers adapted to identify a task requesting service by the central processing unit; an arbitration... | 06/28/2005 |
| 6910022 | Usage rights grammar and digital works having usage rights created with the grammar A system for associating usage rights with digital content. Usage rights are created from a grammar. The usage rights specify a manner of use indicating one or more stated purposes for which the digital content can be at least one of used and distributed by an autho... | 06/21/2005 |
| 6910088 | Bus arbitration using monitored windows of time A method for use with a computer system includes permitting a first bus agent to access a bus during predetermined windows of time and preventing a second bus agent from accessing the bus outside of the windows. The first bus agent has a higher priority than the sec... | 06/21/2005 |
| 6910116 | Game disk layout A software tool automatically places files and folders of a software program within segments of a DVD. The segments are defined by security placeholders, and the disposition of the placeholders is initially randomly determined, consistent with predefined rules. The ... | 06/21/2005 |
| 6907491 | Methods and structure for state preservation to improve fairness in bus arbitration Methods and structure for enhanced bus arbitration providing a hybrid arbitration technique combining priority-based arbitration with round-robin arbitration within a priority level with improved fairness for all devices participating the a round-robin arbitration a... | 06/14/2005 |
| 6907487 | Enhanced highly pipelined bus architecture A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequen... | 06/14/2005 |
| 6904481 | Bus sequence operation with automatic linking from current I/O information to subsequent I/O information In a computer system, a bus adapter processes bus operation information structures for performing bus operations by automatically starting processing each bus operation information structure after completing processing the previous bus operation information structur... | 06/07/2005 |
| 6901487 | Device for processing data by means of a plurality of processors A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per memory. The buses are interconnected by at least one bridge. A processor... | 05/31/2005 |
| 6901469 | Communication control apparatus using CAN protocol A communication control apparatus for performing an arbitration when a collision of frames occurs on a bus has a plurality of message boxes. Each message box stores at least a message for a transmission purpose and an identification code indicative of both a priorit... | 05/31/2005 |
| 6901459 | PROTOCOL FOR TRANSMITTING A PLURALITY OF MULTIPLE EXCHANGE LOGIC FLOW OF COMMAND/RESPONSE PAIRS ON A SINGLE PHYSICAL EXCHANGE CHANNEL BETWEEN MASTER AND SLAVE AND CORRESPONDING SYSTEM FOR CONTROLLING AND MONITORING EXECUTION OF APPLETS An existing active base logic flow between a master transceiver and a slave transceiver, is selected as reference logic flow wherein is generated a set of concurrent logic flows. The concurrent logic flows are built with successive elementary packets segmenting pair... | 05/31/2005 |
| 6901468 | Data storage system having separate data transfer section and message network having bus arbitration A system interface includes a plurality of first directors, a plurality of second directors, a data transfer section and a message network. The data transfer section includes a cache memory. The cache memory is coupled to the plurality of first and second directors.... | 05/31/2005 |
| 6898600 | Method, system, and program for managing database operations Provided are a method, system, and program for performing database operations. A request is received to access database resources from a client over a network. An entry is added to a monitor list indicating a last access time to the database by the client, wherein t... | 05/24/2005 |
| 6886063 | Systems, devices, structures, and methods to share resources among entities Systems, devices, structures, and methods are provided to allow resources to be shared among a plurality of processors. An exemplary system includes a mechanism to grant exclusive control of a resource to a processor, while at the same time, the fast memory of such ... | 04/26/2005 |
| 6880028 | Dynamic request priority arbitration A system and method are provided for dynamically determining the priority of requests for access to a resource taking into account changes in the access needs of a requesting agent over time. A requesting agent selects a priority level from a plurality of priority s... | 04/12/2005 |
| 6877052 | System and method for improved half-duplex bus performance A method for dynamic preemption of read returns over a half-duplex bus during heavy loading conditions involves asserting a preempt signal by a first agent to indicate that the first agent has a read request pending for transmission over the half-duplex bus. A secon... | 04/05/2005 |
| 6877053 | High performance communication architecture for circuit designs using probabilistic allocation of resources A circuit comprising a plurality of components sharing at least one shared resource, and a lottery manager. The lottery manager is adapted to receive request for ownership for the at least one shared resource from a subset of the plurality of components. Each of the... | 04/05/2005 |
| 6877056 | System with arbitration scheme supporting virtual address networks and having split ownership and access right coherence mechanism A computer system may include several client devices, a data network configured to transmit data packets between the client devices, a coherency mode storage unit configured to store an indication to control whether a given address packet is transmitted through the ... | 04/05/2005 |
| 6865634 | Method and apparatus for deadlock prevention in a distributed shared memory system A distributed shared memory system having a memory access request transaction queue having a plurality of queue slots prevents occurrences of deadlocks. The distributed shared memory system is implemented in a networked multiprocessor computing system, and includes,... | 03/08/2005 |
| 6865633 | Independent reset of arbiters and agents to allow for delayed agent reset A system includes two or more agents and a distributed arbitration scheme for the bus to which the agents are connected. Thus, an arbiter corresponding to each agent is provided. The arbiters are reset using a first reset signal, while the agents are reset using a s... | 03/08/2005 |
| 6865632 | Method and apparatus for arbitration and fairness on a full-duplex bus using dual phases A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means. ... | 03/08/2005 |
