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| Number | Title | Issue Date |
| 7343525 | Method and apparatus of detecting error of access wait signal A method and an apparatus for detecting an error of an access wait signal are disclosed. The method comprises the steps of accessing the input/output (I/O) device according to an I/O control command of the electronic device to access the I/O device; and returning to... | 03/11/2008 |
| 7340542 | Data processing system with bus access retraction A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of... | 03/04/2008 |
| 7308517 | Gap count analysis for a high speed serialized bus A method of optimizing communication over a high-speed serial bus by minimizing the delay between packets transmitted over the bus is disclosed. The method comprises: calculating the round trip delay between PHYs connected on the bus by pinging; a bus manager sendin... | 12/11/2007 |
| 7185133 | Data processor A data processor has a first bus master module, first bus slave module and first bus right arbitrating circuit connected to a first bus, a second bus master module, second bus slave module and second bus right arbitrating circuit connected to a second bus, and a bus... | 02/27/2007 |
| 7162557 | Competition arbitration system A competition arbitration system in which chances for using a resource of a computer such as a bus or the like among devices are fair is provided. Pulses are sequentially generated periodically from a pulse generating circuit. It is assumed that first device outputt... | 01/09/2007 |
| 7120718 | Method for generating interrupt commands in a microprocessor system and relative priority interrupt controller A method for generating interrupt commands for a microprocessor system includes storing interrupts in a pending interrupts register, and storing priority values associated with the stored interrupts in a plurality of priority registers coupled to the pending interru... | 10/10/2006 |
| 7096291 | Method and device for arbitrating bus grant A method for arbitrating a bus grant among a plurality of master devices for access to a shared bus is disclosed. The method includes the steps of starting to accumulatively count time in response to a data transfer request signal outputted by one of the master devi... | 08/22/2006 |
| 7076586 | Default bus grant to a bus agent A system may include two or more agents, one of which may be identified as a default agent. If none of the agents arbitrate for the bus, the default agent may be given a default grant of the bus. If the default agent has information to transfer on the bus, the defau... | 07/11/2006 |
| 7038687 | System and method for high-speed communications between an application processor and coprocessor An application processor and coprocessor communicate data, including command and control data, over a separate high-speed datapath. The data may be formatted into a pixel-stream format suitable for sending over the datapath. The application processor may utilize a g... | 05/02/2006 |
| 7035981 | Asynchronous input/output cache having reduced latency The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication with both a system data bus and a I/O data bus. Similarly, the device in... | 04/25/2006 |
| 7024505 | Fair arbitration method in a distributed arbitration system A method of communicating between an initial device and a target device connected by a plurality of intermediate segments in a distributed arbitration system is provided. The method includes establishing an arbitration timer for a communication request by the initia... | 04/04/2006 |
| 7006520 | System and method of operation for managing data communication between physical layer devices and ATM layer devices A system for managing data communication between physical layer devices and ATM layer devices in a cell based ATM network is disclosed. A plurality of low speed physical layer devices a high speed physical layer device are connected to a bus. A bus interface device ... | 02/28/2006 |
| 7003701 | System for facilitated analysis of PCI bus malfunction In a computer system, which makes an error detectable in case plural PCI target devices respond in one PCI cycle and the PCI protocol has become illicit, a processor 1 is connected over a PCI bus 10 to plural PCI devices a 100 to d 130, e... | 02/21/2006 |
| 6988156 | System and method for dynamically tuning interrupt coalescing parameters A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface. An interrupt handler adjusts dynamic Packet and/or Latency values to control how many packets the interface may accumulate, or how much time the interface may ... | 01/17/2006 |
| 6981130 | Forwarding the results of operations to dependent instructions more quickly via multiplexers working in parallel Multiple register input multiplexors select a respective one of the results generated by operation units, and store the selected results in respective architecture registers as specified by the corresponding instructions (from which the results are generated). A for... | 12/27/2005 |
| 6976120 | Apparatus and method to track flag transitions for DRAM data transfer A method and an apparatus to track transition of a flag signal for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes one or more memory devices, coupled to a data bus, to receive a command signal, wherein the command signal initiates ... | 12/13/2005 |
| 6976121 | Apparatus and method to track command signal occurrence for DRAM data transfer An apparatus and a method to track command signal occurrence for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes an interface to couple to a data bus, the data bus to transfer data between the interface and one or more memory device... | 12/13/2005 |
| 6973524 | Interface for bus independent core The present invention is directed to an interface. An interface system suitable for coupling a first bus interface controller with a second bus interface controller includes a first bus interface controller and a second bus interface controller in which the second b... | 12/06/2005 |
| 6915366 | Computer system with a communication bus A bus has a local section (10a,b) and a shared section (11a,b). An arbiter circuit (16) issues an arbited grant (25) to access the shared section (11a,b) in response to a request (22) to perform a bus ac... | 07/05/2005 |
| 6910088 | Bus arbitration using monitored windows of time A method for use with a computer system includes permitting a first bus agent to access a bus during predetermined windows of time and preventing a second bus agent from accessing the bus outside of the windows. The first bus agent has a higher priority than the sec... | 06/21/2005 |
| 6895462 | Integrated circuit An integrated circuit includes a processor and at least one module and provides registers required for the modules as well as access to these registers. By concentrating the required registers according to the invention in a central register bank, which like the pro... | 05/17/2005 |
| 6889277 | System and method for dynamically tuning interrupt coalescing parameters A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface to suit the workload of the interface. An interrupt handler adjusts dynamic Packet and/or Latency values of the interface to control how many packets the interf... | 05/03/2005 |
| 6877057 | Information handling system with dynamic interrupt allocation apparatus and methodology An information handling system is provided which includes a dynamic interrupt router for balancing interrupt assignments among a plurality of devices requesting interrupt assignments. The system balances interrupt assignments among both fixed devices mounted on the ... | 04/05/2005 |
| 6847862 | Conveyor system A conveying apparatus is provided with a control device for performing infinite rotation control of rotation of a strut or wrist shaft of a robot conveying an article and a drive shaft of a conveyor. The control device comprises a rotary shaft (6) rotationall... | 01/25/2005 |
| 6845418 | Bus system for master-slave device accesses, has multiple pseudo-delayer connected to controllers which delay and output access commands to slave devices for having longer latency periods A bus system and a command delivering method includes (a) delivering a first command to a first slave device, and (b) delivering a second command to a second slave device at a point in time which is less than or equal to a latency time of the second slave device in ... | 01/18/2005 |
| 6795878 | Verifying cumulative ordering of memory instructions A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further com... | 09/21/2004 |
| 6762852 | Print feature selection based on combined features of several printers A computer readable media for use with a computer, the computer readable media bearing software configured to present to a user of the computer an interface with which the user can select from a superset of print features provided by multiple printers; receive from ... | 07/13/2004 |
| 6728809 | Time-out control apparatus, terminal unit, time-out control system and time-out procedure The present invention is built on a time out control apparatus to control the time out when a packet is transferred between terminal units connected to different buses. In the time out control apparatus, delay measuring means measures the delay time required for a r... | 04/27/2004 |
| 6678771 | Method of adjusting an access sequencing scheme for a number of PCI- compliant units coupled to a PCI bus system A method of adjusting an access sequencing scheme for a number of PCI (Peripheral Component Interconnect) compliant units coupled to a PCI bus system on a computer system. These PCI-compliant units are associated respectively with a set of request signals... | 01/13/2004 |
| 6636924 | Multiple port I2C hub A multiport device is configured to recognize each active segment on a bus, and to selectively propagate signals within the device depending upon whether the segment is active. Optimal signal propagation is achieved by invoking the control of the propagat... | 10/21/2003 |
| 6490644 | Limiting write data fracturing in PCI bus systems A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous words. Fracture detection logic senses fracturing of the w... | 12/03/2002 |
| 6477596 | Bus controlling method and apparatus for delaying activation of a bus cycle With respect to design regarding a bus cycle, it has been necessary to consider a data conflict, if an output disable time of a device is long. A bus controlling unit is installed in a processor. In the bus controlling unit, parameters regarding output di... | 11/05/2002 |
| 6275885 | System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues pla... | 08/14/2001 |
| 6272608 | Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals A synchronous dynamic random access memory ("SDRAM") operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and i... | 08/07/2001 |
| 6260080 | System for improving signal quality between CPU and floppy disk drive in notebook computer utilizing pull-up device disposed between terminals connected to control signals and one of power supply potentials A notebook computer for stably operating a floppy disk drive, includes: a floppy disk drive for writing or reading information to or from a floppy disk according to predetermined control signals; a motherboard having a controller generating control signal... | 07/10/2001 |
| 6256694 | Distributed early arbitration A commander module, coupled to a system bus including system bus control request signals and associated with one of the system bus control request signals, including means for determining whether control of the system bus is required and means for request... | 07/03/2001 |
| 6195757 | Method for supporting 11/2 cycle data paths via PLL based clock system A system for improving system cycle time while supporting 11/2 cycle data paths with a PLL based clock system using a communication circuit providing a first mode of operation whereby a first cycle time is obtained, and for allowing use of a second mode o... | 02/27/2001 |
| 6178477 | Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resource The present invention comprises a system for implementing pseudo delayed transactions through a bridge in order to guarantee access to a shared device. The system of the present invention functions in a computer system having a plurality of busses, includ... | 01/23/2001 |
| 6173354 | Method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus A method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus is described. In one embodiment, the method includes detecting a write cycle by an initiator for transmitting data to a device. The method further inclu... | 01/09/2001 |
| 6141713 | Bus arbitrator with a hierarchical control structure A bus arbitration apparatus includes N number of hierarchical arbitrators, wherein each hierarchical arbitrator contained in the lowest hierarchy is connected to p number of the bus request units. Especially the hierarchical arbitrator of each hierarchy h... | 10/31/2000 |
