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| Number | Title | Issue Date |
| 7401066 | Correlation of end-of-line data mining with process tool data mining One embodiment of the present invention is a process tool optimization system that includes: (a) a data mining engine that analyzes end-of-line yield data to identify one or more process tools associated with low yield; and (b) in response to output from the analysi... | 07/15/2008 |
| 7370161 | Bank arbiter system which grants access based on the count of access requests Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and al... | 05/06/2008 |
| 7360002 | Method of arbitrating access to a data bus A method for arbitrating access to a data bus among subscribers or bus devices (Tn 1,Tn 2, . . . ), wherein the bus devices are coupled by at least one arbitration ring (12; 38, 40, 42, 44, 46, 48). The method comprises the following steps: a) r... | 04/15/2008 |
| 7171525 | Method and system for arbitrating priority bids sent over serial links to a multi-port storage device A system including a multi-port storage device (e.g., a disk drive) and at least two users, each user coupled to a port of the storage device by a serial link. The storage device has an operational portion and an interface (including arbitration circuitry) between i... | 01/30/2007 |
| 7149828 | Bus arbitration apparatus and bus arbitration method The present invention is to provide a bus arbitration apparatus and a bus arbitration method not reducing data transfer capability as a whole and preventing a loss of transferred data. It performs the arbitration with priority in response to properties of bus master... | 12/12/2006 |
| 7143219 | Multilevel fair priority round robin arbiter A method and apparatus for controlling access to a plurality of resources based on multiple received requests is provided. The system includes a priority register configured to receive each individual request, determine a priority for the request, and transmit the r... | 11/28/2006 |
| 7096307 | Shared write buffer in a peripheral interface and method of operating A data processing system has a single configurable write buffer within a peripheral interface unit that is shared among multiple peripherals. Configuration registers are dynamically programmed to control criteria for determining whether control of a system bus will ... | 08/22/2006 |
| 7089346 | Method of operating a crossbar switch The present invention relates to a method of operating a crossbar switch (1) having a control logic (2) and n input ports (i—0, . . . , i_n-1) and m output ports (o—0, . . . , o_m-1), wherein inform... | 08/08/2006 |
| 7072988 | Key-based collision detection algorithm for multi-initiator domain validation A method for verifying bus performance in a multiple initiator environment is provided. A first initiator generates a key data pattern including a key header and a pattern. The first initiator then writes the key data pattern to an echo buffer of a target after whic... | 07/04/2006 |
| 7020111 | System for using rapid acquisition spreading codes for spread-spectrum communications A system for rapidly acquiring a spreading code, used in a code division multiple access (CDMA) system comprises a generator for generating a first long code and a second long code, with each long code having a length of N chips. The first long code is different fro... | 03/28/2006 |
| 6967965 | Multi-user network system and method of data communication using enhanced preamble A system and method of data communication for multiple stations using shared communication media within a network. A data communication message structure uses a preamble that includes both source and destination data. The message structure allows use of collision re... | 11/22/2005 |
| 6823412 | System and method for arbitration of a plurality of processing modules Method and apparatus for an arbitrated high speed control data bus system providing high speed communications between microprocessor modules in a complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queui... | 11/23/2004 |
| 6721799 | Method for automatically transmitting an acknowledge frame in canopen and other can application layer protocols and a can microcontroller that implements this method A method for use in a CAN device (e.g., a CAN microcontroller) that includes a processor core, for automatically transmitting an acknowledge message. The method includes the steps of receiving a frame of a multi-frame fragmented message, and automatically transmitti... | 04/13/2004 |
| 6721833 | Arbitration of control chipsets in bus transaction A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second control chips through a bus, the bus comprises a bidirectional bus The firs... | 04/13/2004 |
| 6615302 | Use of buffer-size mask in conjunction with address pointer to detect buffer-full and buffer-rollover conditions in a CAN device that employs reconfigurable message buffers A CAN microcontroller that supports a plurality of message objects, and that includes a CAN processor core, a plurality of message buffers associated with respective ones of the message objects, a CAN/CAL module that processes incoming messages that inclu... | 09/02/2003 |
| 6546508 | Method and apparatus for fault detection of a processing tool in an advanced process control (APC) framework A method and apparatus for providing fault detection in an Advanced Process Control (APC) framework. A first interface receives operational state data of a processing tool related to the manufacture of a processing piece. The state data is sent from the f... | 04/08/2003 |
| 6408219 | FAB yield enhancement system A yield enhancement system organizes defect classification and attribute information into a global classification scheme. The global classes are used to identify defect sources and to generate inspection and review plans. The system accumulates defect inf... | 06/18/2002 |
| 6405272 | System and method for arbitration of a plurality of processing modules An arbitration system which allows communication between a plurality of competing processing modules over a shared communication bus. The system comprises an arbitration line coupled to a controller located on each processing module. When a processing mod... | 06/11/2002 |
| 6223244 | Method for assuring device access to a bus having a fixed priority arbitration scheme Computer-based devices, whether initiators or targets, are assured access to a bus having a fixed priority arbitration scheme (such as a SCSI bus) by assigning to each initiator a "fair share" of the bus bandwidth. This share is defined as a number of byt... | 04/24/2001 |
| 6223239 | Dual purpose apparatus, method and system for accelerated graphics port or system area network interface A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, or as a bridge between a system area network interface and the host bu... | 04/24/2001 |
| 6003103 | Method for attachment or integration of a bios device into a computer system using a local bus Chipset or a device for attachment of the ROM BIOS within the system architecture. Although normally attached to the ISA bus, the ROM BIOS may be attached to an alternate bus (typically a higher-performance bus) located within the system, thereby potentia... | 12/14/1999 |
| 5987551 | Attachment or integration of a BIOS device into a computer system using local bus Chipset or a device for attachment of the ROM BIOS within the system architecture. Although normally attached to the ISA bus, the ROM BIOS may be attached to an alternate bus (typically a higher-performance bus) located within the system, thereby potentia... | 11/16/1999 |
| 5974497 | Computer with cache-line buffers for storing prefetched data for a misaligned memory access In a computer including two buses, a main memory, a write back cache, and a peripheral device, a method and apparatus for providing an inter-bus buffer to support successive main memory accesses from the peripheral device is disclosed. The buffer is inclu... | 10/26/1999 |
| 5856921 | Apparatus and method for intermodular communications using system bus controllers A system bus architecture for intermodular communications is disclosed. The system bus architecture comprises a backplane bus with associated memory and a plurality of control registers. A master system processor module is coupled to the backplane bus via... | 01/05/1999 |
| 5754777 | Apparatus and method for distributed arbitration of shared resources A novel distributed arbitration apparatus in accordance with this invention includes a plurality of electrical devices, such as Industry Standard Architecture (ISA) hub cards, that independently determine availability of a shared resource, such as a bus t... | 05/19/1998 |
| 5751974 | Contention resolution for a shared access bus Data communication stations 10, 12, 14 are connected by way of a shared bus 15 common to all the communication stations. When two stations attempt to access the shared bus simultaneously, a conflict resolution method if used to determine which of the two ... | 05/12/1998 |
| 5706469 | Data processing system controlling bus access to an arbitrary sized memory area A novel data processing system is disclosed. Least significant bits of an address of a to-be-accessed memory of a number corresponding to a minimum specified range of a plurality of to-be-controlled memory areas each specified in an arbitrary size in adva... | 01/06/1998 |
| 5692136 | Multi-processor system including priority arbitrator for arbitrating request issued from processors In a multi-processor system, a priority arbitrator receives a request issued from each of processors, and arbitrates conflicts occurring among the requests. The requests derived from the respective processors are inputted via selectors to fixed priority a... | 11/25/1997 |
| 5586265 | Priority arbitrating interface for a plurality of shared subsystems coupled to a plurality of system processing devices for selective association of subsystem to processing device The electronic postage meter includes a printing unit which is responsive to a plurality of motors for printing of a postage indicia in response to a control circuit. The control circuit is comprised of a programmable microprocessor in bus communication w... | 12/17/1996 |
| 5513372 | Peripheral interface having hold control logic for generating stall signals to arbitrate two read and one write operations between processor and peripheral A peripheral interface unit (PIU) used by a microcontroller or microprocessor core having a pipelined architecture to access peripheral modules across a peripheral bus (PBUS). Data read or write accesses to registers in the core space are decoded and pass... | 04/30/1996 |
| 5506964 | System with multiple interface logic circuits including arbitration logic for individually linking multiple processing systems to at least one remote sub-system A data processing and transmission network includes plural information processing systems and shared sub-systems remote from the information processing systems. Each shared sub-system includes an I/O bus and a plurality of I/O bus interface logic circuits... | 04/09/1996 |
| 5414818 | Method and apparatus for controlling reselection of a bus by overriding a prioritization protocol The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus, where the bus has control and arbitration functions distributed among the devices coupled to the bus, with each device having a fixed priority... | 05/09/1995 |
| 5307466 | Distributed programmable priority arbitration A distributed arbitration scheme for a communications bus wherein the bus interface modules decide among themselves who should next use the bus. The protocol is a common multiprocessor backplane bus interface for supporting multiprocessing, shared memory,... | 04/26/1994 |
| 5283902 | Multiprocessor system having time slice bus arbitration for controlling bus access based on determined delay time among processors requesting access to common bus A method and device operate a system that contains several processors with different priority rankings. The overall system starts its operation as an arbitrating system. The conflict time resulting from a simultaneous request is determined, in each case, ... | 02/01/1994 |
| 5038274 | Interrupt servicing and command acknowledgement system using distributed arbitration apparatus and shared bus Each user of an intercommunication bus is associated with a distinct channel of an arbitration bus and maintains a priority record indicating its current priority status against each other user. During a contention interval each user then seeking to use t... | 08/06/1991 |
| 4779089 | Bus arbitration controller A bus arbitration controller controls access of a plurality of asynchronous potential master devices to a unitary interconnecting bus by forming a distributed state machine of arbitration logic units in each of the potential master devices. Each arbitrati... | 10/18/1988 |
| 4766536 | Computer bus apparatus with distributed arbitration A bus apparatus for interconnecting a plurality of nodes is disclosed. The nodes may comprise processors, input/output subsystems, or the like. Each node maintains a unique priority number; the priority numbers are determined independently by each node. S... | 08/23/1988 |
| 4760515 | Arbitration apparatus for determining priority of access to a shared bus on a rotating priority basis An arbitration apparatus for use within a computer system comprises a plurality of individual arbiters arranged in a particular configuration wherein some individual arbiters are higher in the particular configuration than a specific arbiter and some indi... | 07/26/1988 |
| 4745548 | Decentralized bus arbitration using distributed arbiters having circuitry for latching lockout signals gated from higher priority arbiters A silicon semiconductor wafer containing a plurality of silicon integrated circuits formed therein or attached thereto contains at least one data bus to which some of the circuits are connected. Each of the circuits coupled to the data bus contains an arb... | 05/17/1988 |
| 4454581 | Bus contention circuit A bus contention circuit, is employed for each unit of a system capable of seizing use of a bus, wherein the units are arranged in a priority order. Priority resolution is accomplished by registering a request to seize use of the bus from any unit where e... | 06/12/1984 |
