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| Number | Title | Issue Date |
| 8190803 | Hierarchical bus structure and memory access protocol for multiprocessor systems A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clust... | 05/29/2012 |
| 8140728 | Data packet arbitration system A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data ... | 03/20/2012 |
| 8001164 | Method for providing file information in portable device The methods and apparatuses of the present invention for efficiently providing file information in a portable device with limited screen size. When a plurality of files contain substantially identical file information, the present invention utilizes the file informa... | 08/16/2011 |
| 7930456 | Data packet arbitration system A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring data from the plurality of clients to the data transmission line. Data ... | 04/19/2011 |
| 7502881 | Data packet routing mechanism utilizing the transaction ID tag field A data packet routing mechanism including a plurality of clients for issuing read requests to a host device, the read requests each including a TAG field for identifying which of the plurality of clients issued a particular read request, wherein a completion respons... | 03/10/2009 |
| 7469308 | Hierarchical bus structure and memory access protocol for multiprocessor systems A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clust... | 12/23/2008 |
| 7447817 | Method and system for processing arbitration requests Method and system for arbitrating between plural arbitration requests is provided. The system includes a plurality of first stage arbiters that receive plural arbitration requests and a signal that indicates a previously granted request, wherein the first stage arbi... | 11/04/2008 |
| 7412551 | Methods and apparatus for supporting programmable burst management schemes on pipelined buses Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters, and a plurality of target sub-groups. Each target sub-group includes on... | 08/12/2008 |
| 7383363 | Method and apparatus for interval DMA transfer access A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from writing data to a memory until the memory access controller receives a pe... | 06/03/2008 |
| 7373445 | Method and apparatus for allocating bus access rights in multimaster bus systems A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device is assigned a priority value from an organized priority list of priority values. Requests from at least ... | 05/13/2008 |
| 7363533 | High reliability memory module with a fault tolerant address and command bus A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit ser... | 04/22/2008 |
| 7360002 | Method of arbitrating access to a data bus A method for arbitrating access to a data bus among subscribers or bus devices (Tn 1,Tn 2, . . . ), wherein the bus devices are coupled by at least one arbitration ring (12; 38, 40, 42, 44, 46, 48). The method comprises the following steps: a) r... | 04/15/2008 |
| 7337251 | Information processing device with priority-based bus arbitration The information processing device comprises first and second master circuits and an arbiter for arbitrating access rights to a bus to which the master circuits are connected. The arbiter has storage units retaining information representing priorities of the access r... | 02/26/2008 |
| 7337258 | Dynamically allocating devices to buses Devices are assigned to different buses at development time as well as dynamically during operation, based on actual performance. At development time, bus assignment can be determined based on experiments and direct observation of how devices behave in various confi... | 02/26/2008 |
| 7334075 | Managing transmissions between devices Provided are a method, system, and program for processing a transmission from a first device to a second device. An identification transmission is received including an interface address from the first device. A determination is made as to whether the identification... | 02/19/2008 |
| 7304974 | Supporting a network behind a wireless station An apparatus for supporting a network behind a wireless station includes a gateway that can receive from a wireless station a request for a communications session. The gateway can determine whether to authenticate the communications session, and, in response to dete... | 12/04/2007 |
| 7305507 | Multi-stage round robin arbitration system Round robin arbitration system includes a first round robin arbitration module and a second round robin arbitration module. The first round robin arbitration module has a first bit width. It is configured to partition a plurality of requests into a plurality of bloc... | 12/04/2007 |
| 7302510 | Fair hierarchical arbiter A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to the winning requests, each arbitration mechanism forwards valid request... | 11/27/2007 |
| 7274585 | Methods of operating integrated circuit memory devices Methods of operating an integrated circuit memory device include providing a first address and a first command to the memory device and executing the first command within the memory device. This step of executing the first command is performed concurrently with prov... | 09/25/2007 |
| 7269704 | Method and apparatus for reducing system inactivity during time data float delay and external memory write The invention comprises a system for reducing inactive periods in an integrated circuit. The integrated circuit is coupled to an external peripheral by an external data bus. The integrated circuit has a processor coupled to an internal data bus. The system comprises... | 09/11/2007 |
| 7249242 | Input pipeline registers for a node in an adaptive computing engine Input pipeline registers are provided at inputs to functional units and data paths in a adaptive computing machine. Input pipeline registers are used to hold last-accessed values and to immediately place commonly needed constant values, such as a zero or one, onto i... | 07/24/2007 |
| 7231478 | Programmed access latency in mock multiport memory A computer memory arrangement comprises a first plurality of input port facilities (17–19) that are collectively coupled through a first router facility (32) to selectively feed a second plurality of memory modules (20–24). It furthermore co... | 06/12/2007 |
| 7206462 | Method and system for the detection, comparison and volumetric quantification of pulmonary nodules on medical computed tomography scans A method and system for the automated detection and analysis of pulmonary nodules in computed tomographic scans which uses data from computed tomography (CT) scans taken at different times is described. The method and system includes processing CT lung images to ide... | 04/17/2007 |
| 7200699 | Scalable, two-stage round robin arbiter with re-circulation and bounded latency A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality ... | 04/03/2007 |
| 7191268 | Combined host interface controller for conducting communication between a host system and multiple devices in multiple protocols Described herein are methods and systems for conducting computer system communications with a number of different devices that communicate with the computer system in a number of different protocols via a protocol-shared combination host controller. Combination host... | 03/13/2007 |
| 7191256 | Combined host interface controller for conducting communication between a host system and multiple devices in multiple protocols Described herein are methods and systems for conducting computer system communications with a number of different devices that communicate with the computer system in a number of different protocols via a protocol-shared combination host controller. Combination host... | 03/13/2007 |
| 7174403 | Plural bus arbitrations per cycle via higher-frequency arbiter An arbiter in a bus system arbitrates multiple bus transaction requests in a single bus frequency clock cycle, by operating at a frequency greater than the bus frequency. This allows for two or more arbitration operations in a single bus frequency clock cycle with o... | 02/06/2007 |
| 7174402 | Systems, network devices and methods for highly configurable peer-to-peer communications between network devices communicating via a common bus A system and method are provided for initiating peer-to-peer communications via a network bus. The system includes a bus controller in electrical communication with the network bus for controlling communications on the network bus, such as by transmitting commands o... | 02/06/2007 |
| 7167939 | Asynchronous system bus adapter for a computer system having a hierarchical bus structure A computer system having a hierarchical bus structure that allows decoupling of a local bus from a global bus thereof. Decoupling of the local bus is achieved through use of an asynchronous system bus adapter which includes a local bus adapter for handling transacti... | 01/23/2007 |
| 7165133 | Multiprocessor system having shared buses, prioritized arbitration, and clock synchronization circuitry A multiprocessor system having a plurality of processor elements each of which obtains right to use bus of a first or second shared bus in response to a transfer request for control system data or input/output data and as a master, conducts multiplex-transfer or bur... | 01/16/2007 |
| 7159084 | Memory controller A memory controller, such as a SDRAM controller, forms a queue of memory access requests to maximize efficient use of the bandwidth of the memory data bus. More specifically, the SDRAM controller pre-calculates the number of data bursts required to retrieve all the ... | 01/02/2007 |
| 7152125 | Dynamic master/slave configuration for multiple expansion modules A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of th... | 12/19/2006 |
| 7152137 | Method for exchanging data between a plurality of subscribers by means of a data bus The invention relates to a method for exchanging data between a plurality of subscribers (K1, K2, K3, K) by means of a data bus. The subscribers are located in their totality in at least two spatially and physically separate subordinate data bus... | 12/19/2006 |
| 7149828 | Bus arbitration apparatus and bus arbitration method The present invention is to provide a bus arbitration apparatus and a bus arbitration method not reducing data transfer capability as a whole and preventing a loss of transferred data. It performs the arbitration with priority in response to properties of bus master... | 12/12/2006 |
| 7143211 | Memory configuration with I/O support The invention relates to a method for configuring a memory with I/O support. The aim of the invention is to guarantee the processor and I/O functional units that function in time-critical conditions the appropriate priority for data access, using simple programs. To... | 11/28/2006 |
| 7139266 | Configuring equivalent multi-stage interconnection networks in the bit-permuting style Equivalence among bit-permuting networks and the mechanisms for the conversion between equivalent networks. Multistage switching networks in the bit-permuting type and banyan-type can be classified into equivalence classes. One network can usually be replaced by ano... | 11/21/2006 |
| 7127539 | Statistic method for arbitration A statistic method for arbitration is provided, implementing in an arbitration system comprising a bus, a main controller connected to the bus, and a plurality of peripheral devices able to be accessed by the main controller through the bus. The statistic method for... | 10/24/2006 |
| 7119708 | Apparatus and method for providing visual and hardware addressing information An apparatus and method combine visual addresses and electronic addresses for identification of electronic units. In which, the apparatus is one device per electronic unit. Each device comprises a circuit board encapsulated in a device enclosure, and the circuit boa... | 10/10/2006 |
| 7096303 | Method and apparatus for configuring an integrated bus A configurable bus interface circuit includes an internal bus bridge and an internal circuit. The configurable bus interface circuit also includes an internal I/O circuit couplable to an external circuit, via the internal bus bridge. The configurable bus interface c... | 08/22/2006 |
| 7080176 | Bus control device and information processing system In a bus control device including an external interface, internal units, a memory interface, and an internal bus, the memory interface monitors the usage pattern of the internal bus, and in a case where the internal unit is not using the internal bus, a priority pro... | 07/18/2006 |
