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| Number | Title | Issue Date |
| 7366815 | Method and apparatus for serial communication system capable of identifying slave apparatus using half-duplex channel communication method A serial communication system is provided which performs serial communication between host and slave apparatus using half-duplex channel communication with a serial data signal generated by superimposing a data signal on a clock signal. The host apparatus transmits ... | 04/29/2008 |
| 7359959 | Method and apparatus for using a USB cable as a cluster quorum device A method for obtaining a quorum vote by a first node using a Universal Serial Bus (USB) quorum cable, wherein the USB quorum cable comprises a first end connected to a first node and a second end connected to a second node, including determining whether the USB quor... | 04/15/2008 |
| 7353309 | Bus system, bus manager device, node device, and program for bus manager device In a bus system, in accordance with reservations of transfers of isochronous blocks of data and with requests by the node devices for transfers of ones of the isochronous blocks of data and regular blocks of data, a bus manager generates a schedule of the operating ... | 04/01/2008 |
| 7343430 | Methods and apparatus for improving data integrity for small computer system interface (SCSI) devices A SCSI ID of a SCSI initiator device that has won an arbitration is identified on a SCSI bus and stored in a register at a SCSI device. Subsequently, a SCSI ID of a selected SCSI target device which was selected by the SCSI initiator device is identified on the SCSI... | 03/11/2008 |
| 7328291 | System and method for controlling the service engagement in a data bus system Data bus system and method are provided for controlling service engagements for bus users. At least one bus user provides services and other bus users use these services. A resource manager stores information about the available services and information about the se... | 02/05/2008 |
| 7315909 | Hierarchized arbitration method An arbitration method, for a data bus in an architecture having n functional blocks, regulates access to the bus. The method includes: receiving, at one of plural agents, information from one of the functional blocks via high level primitives. Each agent generates i... | 01/01/2008 |
| 7289438 | Method and device for serial data transmission between a position measuring system and a processing unit A method for serial data transmission between a position measuring system and a processing unit that includes transmitting position data and further data between the position measuring system and the processing unit in serial form as digital data words, transmitting... | 10/30/2007 |
| 7266626 | Method and apparatus for connecting an additional processor to a bus with symmetric arbitration A method and apparatus for adding an additional agent to a set of symmetric agents in a bus-based system is disclosed. In one embodiment, the number of symmetric agents in the system is fixed. An additional agent may monitor the symmetric arbitration of the symmetri... | 09/04/2007 |
| 7254452 | Distributed input/output control systems and methods Apparatus and methods for controlling a system that operates responsive to a plurality of input control signals are disclosed. During operation the system generates a plurality of output status/control signals. A master controller has at least first and second contr... | 08/07/2007 |
| 7203779 | Fast turn-off slow turn-on arbitrator for reducing tri-state driver power dissipation on a shared bus A bus arbitrator for use in a shared bus system in which N bus devices request access to a shared bus. The bus arbitrator slowly activates and rapidly de-activates tristate line drivers coupled to the shared bus. The bus arbitrator comprises: 1) an input interface f... | 04/10/2007 |
| 7158532 | Half duplex link with isochronous and asynchronous arbitration Transactions are scheduled over a half duplex link between a first device, such as an IO unit, and a second device, such as a memory controller. Information flowing over the half duplex link is divided into a plurality of service periods, and an isochronous transact... | 01/02/2007 |
| 7152173 | Method and control apparatus for controlling startup of multiple IDEHDDs The present invention provides a method and a control apparatus (1) for sequentially controlling the spinning up of a number of IDE_HDDs (30) included in one computer or network server. The method and apparatus works by assigning different ID numbers t... | 12/19/2006 |
| 7137118 | Data synchronization hardware primitive in an embedded symmetrical multiprocessor computer An embedded symmetrical multiprocessor system includes arbitration logic that determines which central processing unit has access to shared memory. Upon grant of access, the memory address is stored in a memory address register. An address compare circuit compares t... | 11/14/2006 |
| 7114011 | Multiprocessor-scalable streaming data server arrangement A multiprocessor-scalable streaming data server arrangement in a multiprocessor data server having N processors, N being an integer greater than or equal to 2, includes implementing N NICs (Network Interface Cards), a first one of the N NICs being dedicated to recei... | 09/26/2006 |
| 7107375 | Method for improving selection performance by using an arbitration elimination scheme in a SCSI topology An arbitration elimination scheme for a bus. In a preferred embodiment, a programmable counter determines when a SCSI bus idle condition is reached and when a portion of an arbitration window for the bus has passed without participants. If there are no participants ... | 09/12/2006 |
| 7099972 | Preemptive round robin arbiter A resource allocation arbitration system. The system includes a plurality of storage devices, a plurality of indicators, and a plurality of mask bits. Each storage device stores requests for resources. Each indicator enables indication of a condition in which the re... | 08/29/2006 |
| 7072996 | System and method of transferring data between a processing engine and a plurality of bus types using an arbiter A flexible input/output (I/O) interface allows a processing core to communicate high-speed data with a several different types of interfaces including a Direct Memory Access (DMA) interface and a streaming interface. The I/O interface includes a streaming interface ... | 07/04/2006 |
| 7065595 | Method and apparatus for bus access allocation A method for granting access to a bus is disclosed where a fair arbitration is modified to account for varying conditions. Each bus master (BM) is assigned a Grant Balance Factor value (hereafter GBF) that corresponds to a desired bandwidth from the bus. Arbitration... | 06/20/2006 |
| 7051132 | Bus system and path decision method therefor A bus system and a method of deciding a data transmission path are provided. The bus system includes a plurality of functional blocks; a ring bus which transmits data in a single direction; an arbiter which generates a bus grant signal according to a predetermined a... | 05/23/2006 |
| 7043595 | Data transfer control device Even when an S-PCI bus 1b requests transfer while a P-PCI bus 1a is executing burst transfer, assert of a TRDY# signal for data transfer of the P-PCI side is delayed so that next data transfer of the P-PCI side is completed within 8 clock... | 05/09/2006 |
| 7043656 | Methods and apparatus for extending a phase on an interconnect Interconnect logic performs a transaction on an interconnect. The transaction may include multiple phases and the interconnect logic may include a counter state machine coupled to an interconnect state machine. The counter state machine may assert a signal to the in... | 05/09/2006 |
| 7028124 | Method and apparatus for dual queue head processing of interrupt endpoints A method and apparatus for generating, initializing, and scheduling of two interrupt queue heads to represent a single endpoint are described. In an embodiment, a method includes generating primary and secondary interrupt queue heads to represent a single interrupt ... | 04/11/2006 |
| 7016994 | Retry mechanism for blocking interfaces An improved interface technology is provided that may be applied to PCI (Peripheral Component Interconnect) devices connected to a southbridge. Requests are received from at least one requestor. The request require responses to be sent back to the respective request... | 03/21/2006 |
| 7007122 | Method for pre-emptive arbitration An interface system capable of providing pre-emptive arbitration among multiple agents comprises an interface including at least a first agent and a second agent which share the interface for transferring data, the second agent having priority over the first agent f... | 02/28/2006 |
| 7003605 | Method and system for an improved differential form of transitional coding The present invention provides employing differential transitional encoding with a differential bus. Employing the differential transitional encoding comprises dividing the differential bus into one or more groups comprising four bus lines. Employment of the differe... | 02/21/2006 |
| 7003593 | Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses t... | 02/21/2006 |
| 6996656 | System and method for providing an arbitrated memory bus in a hybrid computing system A computing system having at least one microprocessor and a memory subsystem coupled to the at least one microprocessor. A memory controller is coupled to manage memory transactions between the memory subsystem and the at least one microprocessor. At least one arbit... | 02/07/2006 |
| 6996120 | Methods for improving bus performance and bandwidth utilization of a parallel bus LAN Methods for improving bus performance and bandwidth utilization in a Local Area Network (LAN) are disclosed along with methods fo adapting LANs for use with differing hardware interfaces. The LANs described are based on a parallel bus architecture. Performance super... | 02/07/2006 |
| 6976108 | System on a chip having a system bus, an external bus, and a bus arbiter with programmable priorities for both buses, software, and method for assigning programmable priorities A system on a chip has functional blocks accommodated by at least one system bus, and an external bus for accommodating communication with external blocks. A single multi-jurisdictional bus arbiter has programmable rankings for assigning priorities to requests from ... | 12/13/2005 |
| 6952750 | Method and device for providing a low power embedded system bus architecture The tristateless bus interface communication scheme according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a low power embedded system bus architecture is provided with a b... | 10/04/2005 |
| 6950882 | Control for a plurality of electrical consumers of a motor vehicle A controller for a plurality of electric loads of a motor vehicle has a simple design and flexible applicability and expandability. Each electric load is arranged together with a local computer in a load module and is controlled by the respective local computer with... | 09/27/2005 |
| 6934775 | Operating method for a data bus for several users with flexible timed access The invention relates to an operating method for a data bus for several parties with flexible, timed access. According to the method, the parties are synchronized, the bus messages are sent from the parties in a hierarchical sequence and are sent at least in part, o... | 08/23/2005 |
| 6910088 | Bus arbitration using monitored windows of time A method for use with a computer system includes permitting a first bus agent to access a bus during predetermined windows of time and preventing a second bus agent from accessing the bus outside of the windows. The first bus agent has a higher priority than the sec... | 06/21/2005 |
| 6901487 | Device for processing data by means of a plurality of processors A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per memory. The buses are interconnected by at least one bridge. A processor... | 05/31/2005 |
| 6898766 | Simplifying integrated circuits with a common communications bus When integrating a peripheral, it is common practice to use a fully custom design. Custom designs typically optimize performance, size, and energy usage. However, custom designs are more expensive in terms of testing and development time. Rather than designing an in... | 05/24/2005 |
| 6889276 | Priority mechanism for scheduling isochronous and asynchronous transactions on a shared bus A plurality of asynchronous and isochronous transactions on a shared bus are scheduled such that asynchronous latency is minimized while providing a maximum latency for isochronous transactions. This is accomplished by splitting an allocated shared bus time into fra... | 05/03/2005 |
| 6745273 | Automatic deadlock prevention via arbitration switching A method for controlling arbitration that may be used for a bus. The method generally comprises the steps of (A) controlling a bus mastership for the bus using a first arbitration scheme, (B) controlling the bus mastership using a second arbitration scheme in respon... | 06/01/2004 |
| 6721833 | Arbitration of control chipsets in bus transaction A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second control chips through a bus, the bus comprises a bidirectional bus The firs... | 04/13/2004 |
| 6701399 | Priority mechanism for scheduling isochronous and asynchronous transactions on a shared bus A plurality of asynchronous and isochronous transactions on a shared bus are scheduled such that asynchronous latency is minimized while providing a maximum latency for isochronous transactions. This is accomplished by splitting an allocated shared bus ti... | 03/02/2004 |
| 6587868 | Computer system having peer-to-peer bus bridges and shadow configuration registers A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write commands that include configuration data representing a ran... | 07/01/2003 |
