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"What can be more palpably absurd than the prospect held out of locomotives traveling twice as fast as stagecoaches?"
The Quarterly Review ; March edition, 1825
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| Number | Title | Issue Date |
| 8185679 | Controlling bus access An apparatus that controls access by multiple IP cores to a bus is provided. The apparatus includes a main controller and multiple sub controllers, each of the sub controllers being associated with each IP cores. The main controller switches connection between each ... | 05/22/2012 |
| 8171196 | Serial bus system, node device and input/output card that can be connected to the node device There is described a node device of a serial bus system, a bus system with a node device of this type, and an input/output card. In serial bus system, in which individual node devices can have only a limited address space, and in which a number of input/output cards... | 05/01/2012 |
| 8122172 | Portable information security device The invention discloses a portable information security device in the security field. In order to solve the problem that the USB Key transfers data at low speed and may occupy more CPU resources with USB master/slave protocol, and to meet the demand on development o... | 02/21/2012 |
| 8108581 | Information processing apparatus According to one embodiment, an information processing apparatus including a suspension/resume function includes a bus controller which controls a bus capable of transmitting data at a first transmission speed or a second transmission speed lower than the first tran... | 01/31/2012 |
| 8074004 | Electronic device for contention detection of bidirectional bus and related method An electronic device of detecting contention of a bidirectional bus for avoiding failing to drive a bidirectional bus due to bus contention includes: an output terminal, an input terminal and a data output unit, a timing comparing controller and a comparing unit. Th... | 12/06/2011 |
| 8051233 | Method and system for addressing a plurality of ethernet controllers integrated into a single chip which utilizes a single bus interface A method for processing network data is disclosed and may include receiving data via a single bus interface to which each of a plurality of Ethernet controllers are coupled, where the Ethernet controllers are integrated within a single chip. A particular one of the ... | 11/01/2011 |
| 8051232 | Data storage device performance optimization methods and apparatuses Methods and apparatuses for identifying types of data streams and communicating stream information to improve performance of data storage devices are disclosed. Method embodiments generally comprise identifying one or more isochronous requests among a plurality of r... | 11/01/2011 |
| 8032676 | Methods and apparatuses to manage bandwidth mismatches between a sending device and a receiving device Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communication fabric. Rate logic may couple to the communication fabric. The rate logic is configured to determine a data band... | 10/04/2011 |
| 7979616 | System and method for providing a configurable command sequence for a memory interface device A system and method for providing a configurable command sequence for a memory interface device (MID). The system includes a MID intended for use in a cascade interconnect system and in communication with one or more memory devices. The MID includes a first connecti... | 07/12/2011 |
| 7979615 | Apparatus for masked arbitration between masters and requestors and method for operating the same An apparatus is disclosed for handling multiple requestors desiring access to a resource. The apparatus includes a plurality of masters and a plurality of arbitrators. Each arbitrator is assigned to a different one of the plurality of masters. Also, each arbitrator ... | 07/12/2011 |
| 7975086 | Apparatus for real-time arbitration between masters and requestors and method for operating the same A circuit is provided for handling multiple requestors desiring access to a resource. The circuit includes a plurality of arbitrators and a plurality of masters. Each master is assigned to a different one of the plurality of arbitrators. Each arbitrator is defined t... | 07/05/2011 |
| 7962677 | Bus access moderation system A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplish... | 06/14/2011 |
| 7913010 | Network on chip with a low latency, high bandwidth application messaging interconnect A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus (110), memory communications controllers (106), and bus interface controllers (108); eac... | 03/22/2011 |
| 7913011 | Method and apparatus for employing a second bus controller on a data bus having a first bus controller A method for employing a second bus controller on a data bus having a first bus controller including: (a) recording appearances of predetermined character groups on the data bus; (b) noting patterns of the appearances preceding a qualifying quiet period on the data ... | 03/22/2011 |
| 7904624 | High bandwidth split bus A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing messages to the first bus segment and reading messages from the first ... | 03/08/2011 |
| 7895380 | Communication protocol for sharing memory resources between components of a device In a device, such as a cell phone, memory resource sharing is enabled between components, such as integrated circuits, each of which has memory resources. This may be accomplished by providing an interconnect between the components and constructing transaction units... | 02/22/2011 |
| 7840735 | Can system A CAN system includes a plurality of CAN modules and a CAN bus connecting the CAN modules. In at least one embodiment, a filter device is mounted between at least one CAN module and the CAN bus, by which CAN messages transported via the CAN bus and destined for the ... | 11/23/2010 |
| 7840736 | Bus communication enumeration Provided are a method, system, and program for initializing a processor of a computer system, to enumerate a remote bus and remote devices coupled to the remote bus, as operating components of the computer system. In another embodiment, a controller stores a message... | 11/23/2010 |
| 7822898 | Method and apparatus for border node behavior on a full-duplex bus A method and apparatus relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method for determining and communicating the existence of a hybrid bus is disclosed. A method for determining a path to a senior border... | 10/26/2010 |
| 7797472 | Method and apparatus for providing overlapping defer phase responses A multiprocessor system in which a defer phase response method is utilized that allows for a deferring agent to interrupt the normal flow of bus transactions once it gains control of system interface bus. The deferring agent is allowed to look ahead to determine if ... | 09/14/2010 |
| 7774529 | Bus communication apparatus that uses shared memory Bus transfer efficiency is improved in bus communication that uses a shared memory, based on a communication origin master 101 selectively using an arbitration completion notification signal and a memory access completion notification signal. Based on the arb... | 08/10/2010 |
| 7769932 | Bitwise arbitration on a serial bus using arbitrarily selected nodes for bit synchronization A plurality of nodes are coupled via a serial data bus A transition from a first state to a second state is repeatedly transmitted onto the bus from a node arbitrarily selected from the plurality of nodes and is defined as the bit master. One or more of the nodes tr... | 08/03/2010 |
| 7730244 | Translation of commands in an interconnection of an embedded processor block core in an integrated circuit Command translation of burst commands is described. A slave processor local bus (“PLB”) bridge, part of a processor block core embedded in a host IC, has a data size threshold to allow access to a crossbar switch device. A master device, coupled to the slave PLB... | 06/01/2010 |
| 7715182 | Drive box A rack mount drive blade system having a chassis and a drive blade. The chassis has at least one blade bay to accept a drive blade, where the chassis accepts the drive blade into the blade bay with the drive blade in a horizontal orientation. Each blade bay has chas... | 05/11/2010 |
| 7694049 | Rate control of flow control updates Various embodiments adjust the rate at which periodic flow control updates are transmitted when in a lower power or power saving state. One embodiment transmits flow control updates across a bus based upon a first rate in response to a normal power mode and transmit... | 04/06/2010 |
| 7660925 | Balancing PCI-express bandwidth Mechanisms for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the ava... | 02/09/2010 |
| 7634603 | System and apparatus for early fixed latency subtractive decoding Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus... | 12/15/2009 |
| 7631129 | Computer monitoring system and monitoring method An exemplary computer monitoring system includes a central processing unit (CPU) connected to a computer, a first microprocessor, a second microprocessor, and a select switch connected to a terminal device. The CPU is connected to the select switch via the first mic... | 12/08/2009 |
| 7610421 | Bus request control circuit A bus request control circuit provided in a signal processing circuit having a higher priority in an arbitration circuit includes a request signal transmitting section which transmits a request signal to request a bus right to the arbitration circuit. A request ackn... | 10/27/2009 |
| RE40921 | Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the ... | 09/22/2009 |
| 7543094 | Target readiness protocol for contiguous write A method of performing contiguous write transactions on a processor bus according to an embodiment of the present invention includes detecting, by a bus agent, a request for a write cycle, asserting, by the bus agent, a target ready signal for one clock cycle in res... | 06/02/2009 |
| 7519751 | Method of generating an enable signal of a standard memory core and relative memory device A memory device is configured for communicating with one of two different serial protocols, respectively an LPC or an SPI protocol, as well as with a parallel communication protocol through a multi-protocol interface while requiring only a single additional pin as c... | 04/14/2009 |
| 7519752 | Apparatus for using information and a count in reissuing commands requiring access to a bus and methods of using the same In a first aspect, a first method of reissuing a command involving bus access is provided. The first method includes the steps of (1) storing information associated with commands that are to be reissued, wherein the commands are each associated with respective input... | 04/14/2009 |
| 7475176 | High bandwidth split bus A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing messages to the first bus segment and reading messages from the first ... | 01/06/2009 |
| 7467245 | PCI arbiter A bus arbiter that ensures high priority transfers complete and allows high-priority data transfers with specific latency requirements, such as 802.11 requirements, to be prioritized above data transfers with lower latency requirements. As an example, the arbiter cl... | 12/16/2008 |
| 7457901 | Microprocessor apparatus and method for enabling variable width data transfers A microprocessor including processor logic and sparse write logic which asserts address signals and request signals to provide an address and a request for a cache line memory write transaction, which provides one of multiple sparse memory write transactions on the ... | 11/25/2008 |
| 7444456 | SRAM bus architecture and interconnect to an FPGA An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connect... | 10/28/2008 |
| 7441059 | Method and device for data communication A device for data communication between a first host device or a further host device and at least one client device along a shared transmission path includes a first host device, which includes a host application; at least one further host device, which includes a h... | 10/21/2008 |
| 7429990 | Network management card for use in a system for screen image capturing A network management card is provided to capture a screen image of a host system for transmission over a computer network for remote viewing and remote system management. The network management card is provided with a processor which processes a program to implement... | 09/30/2008 |
| 7428607 | Apparatus and method for arbitrating heterogeneous agents in on-chip busses A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is det... | 09/23/2008 |
