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| Number | Title | Issue Date |
| 4916659 | Pipeline system with parallel data identification and delay of data identification signals A pipeline system which is suitable for the processing of data accompanied by data identifying signals comprises interconnected modules which process the data and which controllably transfer the data to one another. Data processing in a module introduces ... | 04/10/1990 |
| 4897784 | Multi-level bus access for multiple central processing unit A system by which a number of central processing units (CPU's) may be used completely independently of one another, and yet by which any CPU within the system may communicate with any other CPU in the system. The implementation of the system requires each... | 01/30/1990 |
| 4882704 | Hand-shake type data transfer control circuit A hand-shake type control circuit for controlling a data transfer circuit according to the status of a data transfer request signal. The data transfer request signal is initially received at a NAND gate and is also directly coupled to the reset input of a... | 11/21/1989 |
| 4864291 | SCSI converter A converter for coupling a single-ended and a differential SCSI bus that facilitates the use of the ARB, SELECTION, and RESELECTION phases of the SCSI protocol.... | 09/05/1989 |
| 4855901 | Apparatus for transferring data between a microprocessor and a memory Data are asynchronously transferred between a microprocessor and a dynamic memory under the control of a memory controller and a circuit for deriving an internal acknowledgment signal. The internal acknowledgment signal is derived in response to the memor... | 08/08/1989 |
| 4791566 | Terminal device session management protocol The invention provides a new and improved system for transferring information between a host system and a terminal system. A digital data processing system includes a host computer system which runs processors and a terminal system which is connected to t... | 12/13/1988 |
| 4787028 | Multicommunication protocol controller A data processing system which includes a host processor and a plurality of remote processing devices which are coupled to a common communication channel. The system also includes a look-up table storing the sets of instructions for a plurality of communi... | 11/22/1988 |
| 4783733 | Fault tolerant communications controller system The present invention relates to a system for controlling multiple communications lines, so that a computer system can operate with a single component failure. Two processors are used to control two communications controllers and each of the controllers c... | 11/08/1988 |
| 4780814 | Global serial channel for microcontroller The present invention is directed to an onboard multiprotocol communications controller global serial channel ("GSC"). The GSC as disclosed and claimed herein is for use with an 8-bit microcontroller for intelligent communications with peripheral systems ... | 10/25/1988 |
| 4695944 | Computer system comprising a data, address and control signal bus which comprises a left bus and a right bus A computer system comprises a bus for data, address and control signals which is divided into a left bus and a right bus by a first gating device. The gating device has an open state which is character-wise activated by a right bus request transported on ... | 09/22/1987 |
| 4642758 | File transfer scheduling arrangement A method and arrangement for scheduling the transmission of data files among a plurality of interconnected computers is disclosed. When a first computer desires to transmit data files to a second computer, the first sends a short duration message to the s... | 02/10/1987 |
| 4631698 | Interface apparatus An interface apparatus for interconnecting signal lines of a computer connector and a peripheral device connector with non-matching interconnect patterns having mismatched data lines or open inputs on handshake or control lines. A pair of conductive paths... | 12/23/1986 |
| 4509116 | Special instruction processing unit for data processing system A special instruction processor, such as a floating point accelerator processor, that processes a special class of instructions. Each instruction identifies the number of operands to be processed as well as the number of data words required to be transfer... | 04/02/1985 |
| 4502114 | Circuit for reliable data transfer between two central processing units This circuit provides a minimally sized data transfer buffer interface between two central processing units for transferring data blocks of variable size. The circuit provides an indication to one CPU that the other CPU has received all the data words tra... | 02/26/1985 |
| 4495572 | Computer intercommunication system In a system of computers interconnected for communication between any two or more of the interconnected computers, such intercommunication being in packets of information in a standardized format normally at a standardized speed, a standardized location w... | 01/22/1985 |
| 4482948 | Microprocessor bus interchange circuit A bus interchange circuit for use with a microprocessor. Timing, gating, sequencing and storage circuitry provide an interface between a microprocessor and external systems requesting control of the microprocessor's busses.... | 11/13/1984 |
| 4472787 | System for transferring words on a bus with capability to intermix first attempts and retrys A system is disclosed for transferring words from an input source to a computer bus which can issue an acknowledge or a negative acknowledge signal. The system includes registers for storing the words to be transferred. It further includes control circuit... | 09/18/1984 |
| 4451886 | Bus extender circuitry for data transmission The present invention is related to bus extender circuitry for data transmission from a first bus at a first site to a second bus at a second site, includes a first transceiver at the first site, a second transceiver at the second site and a data and cont... | 05/29/1984 |
| 4376982 | Protocol for inter-processor dialog over a communication network A communication system includes a plurality of requestors and a plurality of responders representing resources. A protocol exercised by all elements provides accurate and consistent interconnection of all elements in a system where messages may be delayed... | 03/15/1983 |
| 4310896 | Method of interfacing remote units to a central microprocessor A method for interfacing two remote electronic units uses four lines and a handshaking routine including the steps of: causing the first unit to simultaneously transmit a strobe signal on one of the four lines and a signal representing one bit of the info... | 01/12/1982 |
| 4150438 | Interfaces for connecting coded and non-coded data transmission systems An interface circuit for use in a data transmission system has a first port for connection to a 16 wire data highway of the type proposed by the I.E.C. (International Electrochemical Commission) for the interconnection of instruments, and a second port ca... | 04/17/1979 |
| 4128883 | Shared busy means in a common bus environment A data processing system includes a plurality of data handling subsystems which communicate with each other by means of an interval transfer bus. The subsystems are located at ports along the bus and each is provided with a local bus adapter interconnecti... | 12/05/1978 |
| 4103336 | Method and apparatus for allocating bandwidth on a loop system coupling a CPU channel to bulk storage devices A loop system couples a CPU channel to bulk storage devices via a loop controller and device adapter. The loop system is characterized by equal fixed-length, multi-byte frames, each frame of which being assignable to only one terminal at a time. The syste... | 07/25/1978 |
