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| Number | Title | Issue Date |
| 4839795 | Interface circuit for single-chip microprocessor An interface circuit, having a single-chip microprocessor with program instructions in internal memory, includes switching devices between A-D (Analog to Digital) ports of the microprocessor and ports of the interface circuit for selectively connecting an... | 06/13/1989 |
| 4837680 | Controlling asynchronously operating peripherals A plurality of host processors share access to a peripheral data storage subsystem and each have program means for controlling asynchronous operations of the subsystem. Control blocks in each of the host processors are addressably linked together for enab... | 06/06/1989 |
| 4825404 | Interface system which generates configuration control signal and duplex control signal for automatically determining the configuration of removable modules An interface circuit in a modular electronic system includes duplex control-signal transmission lines. Modules connectable to a controller unit of the system transmit configuration data items by way of the duplex lines to the controller during a first tim... | 04/25/1989 |
| 4788657 | Communication system having reconfigurable data terminals The disclosed communication system enables communications between reconfigurable data terminals and a variety of connected computers, having dissimilar operating parameters, by automatically reconfiguring the operating parameters of the calling terminal t... | 11/29/1988 |
| 4730251 | Automatic I/O address assignment An automatic address assignment system has a plurality of I/O devices coupled to a bus. Each device contains a unique machine-readable identifier which is used to select the device for address assignment. The identifier is a binary bit string. Each bit po... | 03/08/1988 |
| 4727475 | Self-configuring modular computer system with automatic address initialization An initial polling sequence for configuring a modular computer system employing a system bus for interconnecting the CPU and various modules attached to the bus. At the beginning of the polling sequence, a bus base address register in each module is prese... | 02/23/1988 |
| 4701878 | Apparatus for assigning addresses to pluggable modules based on contact configuration In order to feed to pluggable electronic modules addresses for an address-controlled data exchange with a control unit, a module code characterizing the type of module is stored in each module in a first memory. A plug location code is further communicate... | 10/20/1987 |
| 4635192 | Self configuring bus structure for computer network A computer bus structure includes a plurality of separate bus segments on a mother board. Plugging in of each of a plurality of interface boards automatically connects the right-hand portion of a particular bus segment to the left-hand portion of an adjac... | 01/06/1987 |
| 4633392 | Self-configuring digital processor system with logical arbiter A digital processor system including several function modules where each modules includes circuitry to perform at least one computational task and circuitry to transfer information containing that module's respective computational task capability to a log... | 12/30/1986 |
| 4578773 | Circuit board status detection system In an electronic system, such as a digital data processing system, comprising a number of circuit boards, each circuit board being of a particular functional type and also uniquely identifiable by a manufacturing revision number, there is provided a statu... | 03/25/1986 |
| 4564899 | I/O Channel bus A data bus system utilizing logical transfer channels provides high data rates (even over long distances) and good error detection. The basic function of a transfer channel is to enable temporary assignment of some portion of the bus resource to a specifi... | 01/14/1986 |
| 4562535 | Self-configuring digital processor system with global system A digital processor system including several function modules where each module includes circuitry to perform at least one computational task and the circuitry to transfer information containing that modules respective computational task capability to a g... | 12/31/1985 |
| 4458357 | Circuit board identity generator A plurality of identical circuit board identification generators are individually located on an associated plurality of circuit boards in a computer system, each generator providing a unique identification for each associated circuit board. Identification... | 07/03/1984 |
| 4445171 | Data processing systems and methods A multiprocessor system intercouples processors with an active logic network having a plurality of priority determining nodes. Messages are applied concurrently to the network in groups from the processors and are sorted, using the data content of the mes... | 04/24/1984 |
| 4380052 | Single transmission bus data network employing a daisy-chained bus data assignment control line which can bypass non-operating stations This disclosure relates to a network of stations having a single transmission bus. A bus assignment control line is daisy-chained to all of the stations to form a closed loop such that an assignment signal will circulate through the loop and return to the... | 04/12/1983 |
| 4354229 | Loop initialization mechanism for a peer-to-peer communication system In a loop-structured communication system interconnecting a plurality of data processors without central controller, stations comprise modems which can start loop operation and achieve synchronous frame transmission around the loop through all participati... | 10/12/1982 |
| 4330825 | Device for automatic control of the storage capacity put to work in data processing systems A device is provided for automatically determining the storage capacity of a data processing or transmission system and signalling when the storage capacity is inadequate to handle an incoming address. The store includes a plurality of storage fractions m... | 05/18/1982 |
| 4286321 | Common bus communication system in which the width of the address field is greater than the number of lines on the bus The technique for transmitting address information between a processor and a plurality of memory subsystems in a common bus communication system. The width of the address field is greater than the number of lines on the bus. For example, addresses are thr... | 08/25/1981 |
| 4268901 | Variable configuration accounting machine with automatic identification of the number and type of connected peripheral units A variable configuration accounting machine having a central processor unit (CPU) of an LSI (Large Scale Integration) microprocessor type and a plurality of peripheral units selectively connectable to the CPU which gives a selected configuration to the ma... | 05/19/1981 |
| 4249240 | Address system for bus interconnected computer system A computer system employs a CPU interconnected to a number of devices and terminals over a common bus. Each device has a different address assigned to it and a message from one device to another, over the bus, is prefixed with the receiving device's addre... | 02/03/1981 |
| 4240143 | Hierarchical multi-processor network for memory sharing A plurality of processors and memory modules arranged in a hierarchy are connected in a network such that memory sharing can occur during processor operations, and control means are provided so as to regulate protected usage of specific areas of the memor... | 12/16/1980 |
| 4133028 | Data processing system having a CPU register file and a memory address register separate therefrom A data processing system having a particular configuration of interconnecting data paths among the data handling units thereof. The central processor unit of the system includes a skew-protected quadriport register file having two read and two write input... | 01/02/1979 |
| 4075693 | Configuration and control unit for a heterogeneous multi-system A configuration and control unit (CACU) is described for a multi-system containing processors, which may be of different types, with heterogeneous channels and local and remote devices, including channel crossbar switches, I/O channel switches, I/O contro... | 02/21/1978 |
