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| Number | Title | Issue Date |
| 7177786 | Implementing a model on programmable hardware A computer-implemented system and method for generating a hardware implementation of graphical code. The method comprises first creating a graphical program. A first portion of the graphical program may optionally be compiled into machine code for execution by a CPU... | 02/13/2007 |
| 7177964 | Multiple removable non-volatile memory cards serially communicating with a host Two or more very small encapsulated electronic circuit cards to which data are read and written are removably inserted into two or more sockets of a host system that is wired to the sockets. According to one aspect of the disclosure, command and response signals are... | 02/13/2007 |
| 7174397 | Information processing apparatus that displays image data An information processing apparatus includes a first system and a second system. The first system includes a CPU capable of executing an operating system, a first display controller that causes a display device to display data, a peripheral device having an interfac... | 02/06/2007 |
| 7174446 | System and method for managing the boot sequence of an information handling system A method and system for maintaining a boot sequence in bootable devices is disclosed. The method includes receiving a bootable device configuration for one or more bootable devices in an information handling system, comparing the bootable device configuration to a c... | 02/06/2007 |
| 7173877 | Memory system with two clock lines and a memory device The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a fir... | 02/06/2007 |
| 7174409 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 02/06/2007 |
| 7174400 | Integrated circuit device that stores a value representative of an equalization co-efficient setting An integrated circuit device is described. The integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may... | 02/06/2007 |
| 7171499 | Processor surrogate for use in multiprocessor systems and multiprocessor system using same A processor surrogate (320/520) is adapted for use in a processing node (S1) of a multiprocessor data processing system (300/500) having a plurality of processing nodes (P0, S1) coupled together and to a plurality of input/output d... | 01/30/2007 |
| 7171505 | Universal network interface connection An interface connection is described for joining a host device, such as a Network Processor, to peripherals such as modems, printers, local area networks, Ethernets and Token-Ring interfaces. The connection is particularly useful for joining portable computers, such... | 01/30/2007 |
| 7171569 | Apparatus, method and program product for preventing system mode change by mistaken instruction An information processing apparatus that allows the operating mode of a system to be changed according to the input of a user instruction includes a request signal obtaining module for obtaining a change request signal for requesting the change of the operating mode... | 01/30/2007 |
| 7171496 | Data bus width conversion apparatus and data processing apparatus A data bus width conversion apparatus is provided for receiving N-bit data from a first device having a first bus width and outputting the N-bit data to a second device having a second bus width. The first device divides the N-bit data into a plurality of bit data g... | 01/30/2007 |
| 7167941 | Multi-port device configuration A method and an apparatus to configure a multi-port device are disclosed. The method includes defining a first set of pointers, one for each port of the multi-port device, and storing the first set of pointers in one or more capability structures of the multi-port d... | 01/23/2007 |
| 7167975 | Wireless Universal Serial Bus link for a computer system A computer system having transceivers coupled to USB ports so as to provide a wireless USB bus between a computer and one or more peripheral devices is disclosed. The transceivers allows the computer to be remotely located from the peripheral devices (e.g., USB devi... | 01/23/2007 |
| 7168029 | Method for testing a universal serial bus host controller A chip test method is suitable for testing a universal serial bus host controller. First, the host controller and the client device are individually set in a test mode. Next, the client device performs a client-side test preparation action. In addition, the host con... | 01/23/2007 |
| 7167930 | Centralized queue in network printing systems A centralized queue for a network printing system allows clients to make job requests and be placed in a job queue without transmitting the actual print job data to the network. An imaging device protocol (IDP) operates independently of the network layers below and ... | 01/23/2007 |
| 7167929 | Integrated-circuit implementation of a storage-shelf router and a path controller card for combined use in high-availability mass-storage-device shelves that may be incorporated within disk arrays, and a storage-shelf-interface tunneling method and system An integrated circuit implementing a storage-shelf router, used in combination with path controller cards and optionally with other storage-shelf routers, to interconnect SATA disks within a storage shelf or disk array to a high-bandwidth communications medium, such... | 01/23/2007 |
| 7165136 | System and method for managing bus numbering Bus numbering management for an information handling system, such as a personal computer, is provided by interfacing one or more selectively hidden devices with one or more buses through either a hardware or software implementation. If an inactive bus becomes active... | 01/16/2007 |
| 7165109 | Method and system to access software pertinent to an electronic peripheral device based on an address stored in a peripheral device A method and system for obtaining a network address stored in a peripheral device, and accessing a remote device at the network address to obtain information related to the peripheral device. When the peripheral device is connected to a host computer, the stored net... | 01/16/2007 |
| 7165128 | Multifunctional I/O organizer unit for multiprocessor multimedia chips An apparatus and method for providing enhanced performance for multi-processor multimedia chips. In one embodiment, the present invention is comprised of a data and communication apparatus coupled with the multimedia system in which the multi-processor multimedia ch... | 01/16/2007 |
| 7165133 | Multiprocessor system having shared buses, prioritized arbitration, and clock synchronization circuitry A multiprocessor system having a plurality of processor elements each of which obtains right to use bus of a first or second shared bus in response to a transfer request for control system data or input/output data and as a master, conducts multiplex-transfer or bur... | 01/16/2007 |
| 7161948 | High speed protocol for interconnecting modular network devices A network switch for network communications is disclosed. The switch includes a first data port interface, supporting at least one data port transmitting and receiving data at a first data rate and a second data port interface, supporting at least one data port tran... | 01/09/2007 |
| 7162567 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 01/09/2007 |
| 7162625 | System and method for testing memory during boot operation idle periods The present invention discloses an information handling system that reduces POST time in a boot operation. The information handling system includes a processor, a memory and a BIOS unit. The BIOS also includes memory test pointer and a test block size indicator. Dur... | 01/09/2007 |
| 7162554 | Method and apparatus for configuring a peripheral bus A method an apparatus for providing capability information to a shared controller. In one embodiment, a peripheral bus host controller may be shared by a plurality of peripheral devices coupled to a peripheral bus. The peripheral devices may include coder/decoder (c... | 01/09/2007 |
| 7162563 | Semiconductor integrated circuit having changeable bus width of external data signal A data controlling unit activates a predetermined number of data terminals according to a mode signal and changes a bus width of external data signal. According to the mode signal, an address controlling unit selects a predetermined number of bits of an internal add... | 01/09/2007 |
| 7162395 | Cospas-sarsat beacon tester in a removable expansion card for a handheld computing device A remote tester for a radio frequency beacon includes a plug-in module insertable into a cooperating slot in a handheld computing device so as to communicate data between the module and the computing device, wherein the module includes an antenna, at least one radio... | 01/09/2007 |
| 7162376 | Circuits, systems and methods for dynamic reference voltage calibration A system comprises a master device and a plurality of memory devices coupled to the master device by an interconnect in an embodiment. The master device obtains a plurality of values representing reference voltage values and selects a first value in the plurality of... | 01/09/2007 |
| 7161400 | Phase synchronization for wide area integrated circuits A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signa... | 01/09/2007 |
| 7161935 | Network fabric management via adjunct processor inter-fabric service link An adjunct processor controls an inter-fabric service link (IFSL) coupled to at least two independent SAN switching networks. The inter-fabric service link is coupled between multiple switching fabrics to allow the attached switching fabrics to be logically managed ... | 01/09/2007 |
| 7162306 | Internal medical device communication bus In general, the invention facilitates improved inter-module communication within a medical device system, such as an automated external defibrillator (AED), by using a serial data interface based on the USB specification to transfer data between modules. As a result... | 01/09/2007 |
| 7159017 | Routing mechanism for static load balancing in a partitioned computer system with a fully connected network A mechanism for balancing message traffic in a multi-chassis fully interconnected computer system partitioned into multiple domains allows the system to identify I/O transactions, to route I/O transactions over inter-domain cables, and to route non-I/O transactions ... | 01/02/2007 |
| 7158927 | System and method for the logical substitution of processor control in an emulated computing environment In an emulated computing environment, a method is provided for logically decoupling the host operating system from the processor of the computer system with respect to certain processor settings of the processor. A hypervisor of the emulation program replaces some o... | 01/02/2007 |
| 7158483 | Communication node and communication terminal The disclosed communication node has a function for recognizing one communication node on the first network as one of constituent elements in own communication node, and a function for disclosing an own configuration information regarding the constituent elements as... | 01/02/2007 |
| 7158536 | Adaptive-allocation of I/O bandwidth using a configurable interconnect topology Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, ... | 01/02/2007 |
| 7159018 | System and method for installing software onto a built-to-order computer system using an identification device A system including a server, a computer system, and a device coupled to a port of the computer system is provided. The server includes a script associated with an identifier. The device includes the identifier. The computer system is configured to read the identifie... | 01/02/2007 |
| 7158422 | System and method for communicating information to a memory device using a reconfigured device pin A system and method for communicating information to and from memory deices. In one embodiment, the invention includes a memory system having a memory device having at least one extraneous device pin, a memory controller configured to control the memory device and a... | 01/02/2007 |
| 7159104 | Simplified memory detection Automatic recognition of the type of memory within a device package by using strap resistors within the device package. Such recognition enables a processor, such as a GPU, to automatically configure itself to work with the memory. A device package includes a strap ... | 01/02/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7159046 | Method and apparatus for configuring communication between devices in a computer system A control hub includes a first interface and a second interface to transfer data. The first interface connects to a first bus. The second interface connects to a peripheral bus. The control hub receives configuration address and configuration data during a configura... | 01/02/2007 |
| 7159135 | Method and apparatus for controlling a multi-mode I/O interface to enable an I/O buffer to transmit and receive data according to an I/O protocol In some embodiments, a method and apparatus for a multi-mode I/O interface are described. In one embodiment, the interface includes a transmit state machine that generates a state signal indicating a state of the I/O interface in a next clock cycle. A pattern genera... | 01/02/2007 |
