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| Number | Title | Issue Date |
| 7251717 | Semiconductor memory device While a plurality of physical address memories are provided with respect to one logical address of a non-volatile memory device, an empty physical address memory contained in the plural physical address memories is searched with respect to a writing operation for on... | 07/31/2007 |
| 7249237 | Control method for data transfer control unit An upper-level host has a control unit and a host controller for controlling the operation of a device. The host controller includes a buffer memory that reads data from the device into the buffer memory. The control unit reads data from the buffer memory and handle... | 07/24/2007 |
| 7249236 | Method and system for controlling memory accesses to memory modules having a memory hub architecture A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules... | 07/24/2007 |
| 7249220 | Storage system To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data caching control units are connected to each other through an interconnectio... | 07/24/2007 |
| 7248838 | Wireless communication system within a system on a chip A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the tra... | 07/24/2007 |
| 7249167 | Intelligent modular server management system for selectively operating a plurality of computers An intelligent, modular server management system for coupling a series of remotely located computers to one or more user stations allowing for selective access of the remotely located computers. A centralized computer matrix switching system is provided to enable a ... | 07/24/2007 |
| 7249201 | Single driver for multifunctional SCSI chips A method is provided for managing multiple functions of a multi-channel SCSI chip. The method includes hiding a first function of a multi-channel SCSI chip from an operating system, wherein the first function corresponds to a first channel of the multi-channel SCSI ... | 07/24/2007 |
| 7246188 | Flow control method to improve bus utilization in a system-on-a-chip integrated circuit A system-on-chip (SoC) integrated circuit (IC) has reduced bus contention and improved bus utilization. The SoC IC includes a bus controller. Masters interconnected with the bus controller issue requests for data and receive requested data in response to the request... | 07/17/2007 |
| 7245145 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 07/17/2007 |
| 7246186 | Mobius time-triggered communication In one embodiment, a node comprises a first network interface and a second network interface. The node further comprises a first bus guardian that asserts a first bus guardian signal when the second network interface is allowed to transmit and a second bus guardian ... | 07/17/2007 |
| 7246189 | Method and apparatus for enhancing universal serial bus A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB spe... | 07/17/2007 |
| 7246213 | Data address security device and method Methods and devices for monitoring transactions on a bus are disclosed herein. An embodiment of the device comprises a memory component and a comparator component. The memory component stores at least one address. The comparator component is operatively connected to... | 07/17/2007 |
| 7243217 | Floating point unit with variable speed execution pipeline and method of operation A variable speed floating point unit comprising: 1) an execution pipeline comprising a plurality of execution stages capable of executing floating point operations in a series of sequential steps; and 2) a clock controller capable of receiving an input clock signal ... | 07/10/2007 |
| 7243175 | I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can ... | 07/10/2007 |
| 7243167 | Managing peripheral device address space resources using a tunable bin-packing/knapsack algorithm Methods and systems for allocating address space resources to resource requesting peripheral devices in an efficient manner. Resource requests are gathered for enumerated peripheral devices host by a computer platform. A map containing resource alignment requirement... | 07/10/2007 |
| 7242213 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 07/10/2007 |
| 7242218 | Techniques for combining volatile and non-volatile programmable logic on an integrated circuit Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second bloc... | 07/10/2007 |
| 7243158 | Method, system and computer program for identification of data and translation of data between storage locations A method for configuration of a data lens for use in translation of information between first information located in a first information storage location and stored in a first information format and a second information stored in a second information storage locatio... | 07/10/2007 |
| 7239636 | Multiple virtual channels for use in network devices A method for establishing a virtual channel between network devices is disclosed. In the case of a local network device establishing a virtual channel with a remote network device, a virtual channel request message is sent from the local network device to the remote... | 07/03/2007 |
| 7240130 | Method of transmitting data through an 12C router A method of transmitting data through an I2C router from a source port to a destination port, the method comprising: receiving data in a first I2C source port buffer of the I2C router; capturing the I2C destination port before the first I2C source port buffer has ov... | 07/03/2007 |
| 7236987 | Systems and methods for providing a storage virtualization environment A storage virtualization environment is provided that includes a system for providing one or more virtual volumes. The system may include a host system and a set of storage devices, each of which includes physical block addresses that stores data. Further, the syste... | 06/26/2007 |
| 7237073 | Memory system having data inversion and data inversion method for a memory system A memory system and a method of reading and writing data to a memory device provide byte-by-byte write data insertion without adding extra pins or balls to the packaged device. Accordingly, the high frequency performance of the device can be improved. ... | 06/26/2007 |
| 7236979 | Menu-less system and method for interactively manipulating and reformatting data entered in a tabular format in a data processing application The present invention is directed at a simplified system and method for manipulating data in a data processing application. The system and method allow the user to manipulate data in a table-like manner without resorting to other data entry screens or windows to def... | 06/26/2007 |
| 7237135 | Cyclemaster synchronization in a distributed bridge A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon occurrence of a cycle synchronization event on the local portal; the pe... | 06/26/2007 |
| 7237152 | Fail-operational global time reference in a redundant synchronous data bus system Methods and apparatus are provided for a fail-operational global time reference for a synchronous redundant data bus including multiple pluralities of timing servers cross-coupled between a plurality of buses in said redundant synchronous data bus system, the appara... | 06/26/2007 |
| 7234041 | Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer when a system bus is in a data access phase. When a processor generates... | 06/19/2007 |
| 7234029 | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculativ... | 06/19/2007 |
| 7234070 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 06/19/2007 |
| 7234013 | System and method for preventing wake on LAN to protect expansion cards Embodiments of the present invention include a method for providing protected swapping of a peripheral component in a computer system. The method comprises determining a position of a first mechanical retention latch wherein the first mechanical retention latch has ... | 06/19/2007 |
| 7233977 | Messaging mechanism employing mailboxes for inter processor communications A shared resources service processor facilitates messaging between line processors and provides a single point of contact for a user interfacing with line processor(s), for example in a storage system interface. Shared memory is divided into “mailboxes” that are... | 06/19/2007 |
| 7233167 | Block symmetrization in a field programmable gate array An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block ... | 06/19/2007 |
| 7233336 | Systems and methods for capturing screen displays from a host computing system for display at a remote terminal The present invention provides systems and methods for monitoring a host computing system from a maintenance computing system located at a remote location. The system of the present invention includes a frame grabber that is connected the digital output of a video c... | 06/19/2007 |
| 7234016 | Information processing apparatus, information processing method and information processing program To provide an information processing apparatus and the like, in which even when a plurality of other information processing apparatuses are connected on a single serial bus system, a required one of the information processing apparatuses can be rapidly and easily se... | 06/19/2007 |
| 7233972 | Method and apparatus for coordination of client/server processes The invention provides for the coordination of client/server processes. One or more embodiments provide a completion object comprised of various states of completion of a client request. The completion object may be manipulated to transition from one state to anothe... | 06/19/2007 |
| 7228366 | Method and apparatus for deterministic removal and reclamation of work items from an expansion bus schedule A method and apparatus for deterministic removal and reclamation of work items from an expansion bus schedule are disclosed herein. A work item is removed from an enabled expansion bus schedule data structure and a coherency signal is then generated utilizing an exp... | 06/05/2007 |
| 7227382 | Transmit based equalization using a voltage mode driver A driver circuit. In one embodiment, the driver circuit includes a plurality of pull-up circuits and a plurality of pull-down circuits. The driver circuit also includes control logic that is coupled to activate/deactivate the pull-up and pull-down circuits. The driv... | 06/05/2007 |
| 7227380 | Synchronous first-in/first-out block memory for a field programmable gate array The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plur... | 06/05/2007 |
| 7228374 | Data transmission system for connecting a controller with drives A data transmission system is described that connects a controller with drives in machine tools and production machines. The controller can be connected via an internal data bus with at least one internal drive, wherein the same data bus profiles are used for the in... | 06/05/2007 |
| 7225282 | Method and apparatus for a two-wire serial command bus interface A method for bi-directional transmission of data between a source and a sink over a two-wire interface includes re-mapping a data signal and a clock signal from a first local bus on the source into a different protocol signal. Transmitting the different protocol sig... | 05/29/2007 |
| 7225288 | Extended host controller test mode support for use with full-speed USB devices An extended host controller test mode support is provided. In the example of USB host controllers, an enhanced host controller is provided to control the high-speed traffic. Further at least one companion host controller controls the full-speed and/or low-speed traf... | 05/29/2007 |
