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| Number | Title | Issue Date |
| 4254464 | Common data buffer system A high speed common data buffer system is described for providing an interface and communications medium between a plurality of computers utilized in a distributed computer complex forming part of a checkout, command and control system for space vehicles ... | 03/03/1981 |
| 4245307 | Controller for data processing system A controller for at least one secondary storage device for use in a data processing system having a system bus which accommodates a device or a CPU that first acquires control, a device bus that has the same address, data and control format as the system ... | 01/13/1981 |
| 4237546 | Multi-layered back plane for a computer system The multi-layered back plane of this invention permits a plurality of processors and a plurality of memories to be interleaved through separate memory interface boards in a computer in a manner which provides a significant reduction of path length while e... | 12/02/1980 |
| 4232294 | Method and apparatus for rotating priorities between stations sharing a communication channel A method and apparatus for rotating priorities among stations on a communication channel, and particularly on a contention channel where a plurality of active stations are provided, each capable of seizing use of the channel. Counter means at each station... | 11/04/1980 |
| 4228496 | Multiprocessor system A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send in... | 10/14/1980 |
| 4195351 | Loop configured data transmission system A data transmission system which includes stations connected in a closed loop configuration with interface capabilities at each station to connect to an external data processor. Through this configuration simultaneous transmission of data among processors... | 03/25/1980 |
| 4172283 | Computer system comprising at least two individual computers and at least one system bus bar A computer system comprises at least two individual computers and at least one system bus bar which is composed of a system data bus and a system address bus. In each case, between one of the individual computers and the system bus bar there is arranged a... | 10/23/1979 |
| 4124890 | Microprocessor computing system According to the invention, a microprocessor computing system comprises at least one data processing device and at least one group of execution control elements; said group constitutes a control level and includes at least one microprogram control device ... | 11/07/1978 |
| 4087855 | Valid memory address enable system for a microprocessor system A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adapt... | 05/02/1978 |
| 4035770 | Switching system for use with computer data loop terminals and method of operating same A switching system for use with a plurality of data terminals connected in series in a loop, the ends of which are connected to a central computer so that the central computer may communicate with the data terminals, the system comprising a plurality of s... | 07/12/1977 |
| 4010449 | MOS computer employing a plurality of separate chips A metal-oxide-semiconductor (MOS) computer wherein the bidirectional data bus lines which communicate with the central processing unit (CPU) are also utilized to convey CPU status information to a status latch, thereby eliminating pin connections otherwis... | 03/01/1977 |
| 3984637 | Computer terminal security system This invention is a security system for computer terminals which system provides means for preventing the unauthorized access to digital computers from illicit terminals. The invention provides a local code unit which includes means for manually selecting... | 10/05/1976 |
| 3962684 | Computing system interface using common parallel bus and segmented addressing A computing system includes a central processor unit (CPU) integrated on a monolithic chip, in combination with a plurality of external memory units. The CPU includes a parallel arithmetic logic unit (ALU) and an internal random access memory interconnect... | 06/08/1976 |
| 3938094 | Computing system bus A single parallel bus interconnects the various portions of a central processing unit. Data transmission between the various portions of the processor is based on sequential use of the common bus, and is synchronized by control circuitry. Circuit means ar... | 02/10/1976 |
