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| Number | Title | Issue Date |
| 8090888 | Universal serial bus hub with wireless communication to remote peripheral devices A wireless USB hub for connecting a plurality of remote peripheral devices to a computer for communication therewith without the need to physically connect the peripheral devices to the hub via a cable connection. The wireless USB hub includes a receiver for receivi... | 01/03/2012 |
| 8069287 | Universal serial bus device and method for controlling universal serial bus device An SE0 timer detects that an SE0 state of a universal serial bus continues for 3 ms or more, and asserts an SE03ms detected signal to a suspending/reset discriminating circuit. The suspending/reset discriminating circuit connects a pull-up resis... | 11/29/2011 |
| 8060675 | Computing module with serial data connectivity A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel b... | 11/15/2011 |
| 8024503 | System and method for accessing internet via TV and a PC connecting set and a TV connecting set A system and method of television internet and interactive entertainment, as well as a computer PC box and a television TV box for realizing the television internet and interactive entertainment are provided. Via the computer interface module in the computer PC box ... | 09/20/2011 |
| 8015333 | Method and apparatus for the detection of the end of a daisy chain A method and apparatus for detecting the end of a daisy chain are described. A node receives an M-wide bit input, terminates K bits of the input, shifts and outputs the remaining M-K bits, and drives from the node K bits onto the output. ... | 09/06/2011 |
| 8015334 | Power-on signal transmitting system and power-on signal transmitting method The invention discloses a power-on signal transmitting system, which includes a first electronic device, a second electronic device and a cable coupled between the two electronic devices. The first electronic device includes a power-on control unit. The second elect... | 09/06/2011 |
| 7996590 | Semiconductor memory module and semiconductor memory system having termination resistor units A semiconductor memory module includes a memory module board having at least one semiconductor memory device. The semiconductor memory device includes a data input buffer that receives data and a first reference voltage via first and second input terminals, a comman... | 08/09/2011 |
| 7991931 | Data transport architecture The present invention is a novel device, system, and method for data transport and bus architecture. According to an exemplary embodiment of the present invention, the bus architecture may comprise of a continuous serial bus that may be incorporated into a process c... | 08/02/2011 |
| 7970968 | Apparatus and method for controlling plural functional blocks using common command This invention relates to an information-signal-processing apparatus etc. for performing a series of processing pieces by using plural functional blocks in response to any information signals, in which functions can be easily upgraded through version upgrading of th... | 06/28/2011 |
| 7953912 | Guided attachment of accelerators to computer systems A method of guided attachment of hardware accelerators to slots of a computing system includes dividing a first group of hardware accelerators into a plurality of priority classes, dividing a first group of slots of the computing system into a plurality of hierarchi... | 05/31/2011 |
| 7949809 | Peripheral component interconnect express interface and method for signal processing The present invention discloses a PCI Express interface and a method of signal processing, and particularly relates to the physical coding sub-layer that transmits data between physical media access layer and media access control layer of the PCI Express. The PCI ex... | 05/24/2011 |
| 7945718 | Microcontroller waveform generation One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (3... | 05/17/2011 |
| 7934031 | Reshuffled communications processes in pipelined asynchronous circuits An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data using domino logic, and use the state-holding ability of the domino log... | 04/26/2011 |
| 7930454 | Thin-client terminal and client/server-system having such a terminal A thin-client terminal (1,1′) according to the invention serves for use in a potentially explosive area (ExB) and has at least the following components: an EDP device (11,11′), which can be programmed using software, has graphics capabilities, has ... | 04/19/2011 |
| 7921247 | Sharing a dynamically located memory block between components executing in different processor modes in an extensible firmware interface environment A block of memory is allocated from a volatile memory device, such as a main system random access memory. The memory block is allocated dynamically and has a dynamically assigned memory address. The memory address of the memory block is shared between a master compo... | 04/05/2011 |
| 7917675 | Method and apparatus for interconnecting modules An industrial process control apparatus and method that includes a number of processors and a number of input/output modules. Each processor is connected to a plurality of the input/output modules by a unidirectional command line. Each input/output module is connect... | 03/29/2011 |
| 7913005 | Capacitive multidrop bus compensation The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the band... | 03/22/2011 |
| 7899962 | I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can ... | 03/01/2011 |
| 7899961 | Multi-mode bus inversion method and apparatus In one embodiment, an integrated circuit comprises circuitry for performing bus inversion. The circuitry is operable to configure the integrated circuit to implement one of a plurality of bus inversion schemes each of which the integrated circuit is capable of perfo... | 03/01/2011 |
| 7890682 | Semiconductor storage device and storage system A semiconductor storage device includes an external input/output port. A system bus of a server, which is extended to outside of the server, is connected to the external input/output port directly as a serial interface. ... | 02/15/2011 |
| 7865641 | Synchronization and scheduling of a dual master serial channel One embodiment provides a system including a communications channel, a first channel master, and a second channel master. The first channel master is configured to obtain latency values and maintain a first schedule of data traffic on the communications channel base... | 01/04/2011 |
| 7818483 | Methods and apparatuses for improving SATA target device detection Methods and apparatuses for improving detection of a Serial Advanced Technology Attachment (“SATA”) target device by a storage initiator over a link. The storage initiator receives a Frame Information Structure (“FIS”) and determines whether the FIS is valid... | 10/19/2010 |
| 7774526 | Method for deterministic timed transfer of data with memory using a serial interface A method for improving the speed and efficiency of transmitting data between two components in which the transmitted data is sent, at least partly, through a serial bus is shown. According to the method, the fields in the data frames being transmitted between the co... | 08/10/2010 |
| 7765347 | Console connection A modular computer system (for example a blade server system) includes a plurality of information processing modules (e.g., server blades). Each information processing module can include a processor operable to provide information processing functions and a service ... | 07/27/2010 |
| 7739433 | Sharing bandwidth of a single port SRAM between at least one DMA peripheral and a CPU operating with a quadrature clock A dual or triple access interface (e.g., hardware and software implementation) allows a CPU and at least one DMA peripheral, e.g., Universal Serial Bus (USB) DMA engine, to transfer data in and/or out of a common single port SRAM by negotiating access requests betwe... | 06/15/2010 |
| 7734852 | Modular computer system A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via a plurality of respective high speed serial links (26, 40) such as based on ... | 06/08/2010 |
| 7716401 | Memory module capable of improving the integrity of signals transmitted through a data bus and a command/address bus, and a memory system including the same A memory module and a related memory system are disclosed. The memory module comprises a semiconductor memory having a data output buffer, a data input buffer, a command/address input buffer and a first termination resistor unit connected to a data bus. The memory m... | 05/11/2010 |
| 7716402 | Universal serial bus hub with wireless communication to remote peripheral devices A wireless USB hub for connecting a plurality of remote peripheral devices to a computer for communication therewith without the need to physically connect the peripheral devices to the hub via a cable connection. The wireless USB hub includes a receiver for receivi... | 05/11/2010 |
| 7711877 | Image sensing device An image sensing device includes an image sensing unit, an interface unit, a control endpoint, an isochronous endpoint, a bulk endpoint, an interrupt endpoint, and an interface unit controller. The image sensing unit senses a moving image and a still image. The inte... | 05/04/2010 |
| 7689745 | Mechanism for synchronizing controllers for enhanced platform power management In one embodiment, an apparatus to synchronize multiple controllers is disclosed. The apparatus comprises a plurality of controllers, and logic coupled to the plurality of controllers to control one or more controllers of the plurality of controllers to perform fetc... | 03/30/2010 |
| 7657677 | Blade server system with a management bus and method for managing the same A blade server system with a management bus and method for managing the same. The blade server system includes a connection board and a management module. The connection board is used for modular interconnection, including communication paths for conducting signals ... | 02/02/2010 |
| 7657678 | Modular computer system A modular computer system (20) including a universal connectivity station (UCS) (22) interconnected to a plurality of remote modules (30, 32, 34, 36, 38, 42) via a plurality of respective high speed serial links (26, 40) such as based on ... | 02/02/2010 |
| 7653768 | Method, system, and program for master and slave units connected in daisy chain wherein appended error code is transferred between the units A data transfer method for connecting a master unit on an upstream side and a plurality of slave units on an downstream side in series with serial bus by a daisy chain system and transferring data having an appended error check code or error correction code between ... | 01/26/2010 |
| 7650448 | I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can ... | 01/19/2010 |
| 7647439 | Electronic Warning System A building control or danger warning system includes a two-core circular bus for voltage supply and for communication with bus user circuits connected to the cores of the circular bus. The bus user circuits are looped-into the circular bus via FET (field effect tran... | 01/12/2010 |
| 7644210 | Method and system for storing and retrieving a translation of target program instruction from a host processor using fast look-up of indirect branch destination in a dynamic translation system Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the transla... | 01/05/2010 |
| 7617342 | Universal serial bus dongle device with wireless telephony transceiver and system for use therewith A universal serial bus (USB) dongle device includes a wireless telephony transceiver that receives an inbound RF signal and that generates inbound data based on the inbound RF signal and receives outbound data and that generates an outbound RF signal in response the... | 11/10/2009 |
| 7552257 | Data transmission device with a data transmission channel for the transmission of data between data processing devices The present invention provides a data processing apparatus having at least one dedicated data processing device (10) of a first type, a central data processing device (4) for controlling dedicated data processing devices (10, 12, 14), at least o... | 06/23/2009 |
| 7539800 | System, method and storage medium for providing segment level sparing A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multipl... | 05/26/2009 |
| 7519750 | Linear burst mode synchronizer for passive optical networks The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for reco... | 04/14/2009 |
