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| Number | Title | Issue Date |
| 7908308 | Carry-select adder structure and method to generate orthogonal signal levels A Carry-Select Adder structure comprising a carry generation network and a multiplexer to select a particular pre-calculatad sum of a bit-group via orthogonal signal levels of a Hot-Carry signal provided by said carry generation network (21), wherein in order... | 03/15/2011 |
| 7571204 | M-bit race delay adder and method of operation There is disclosed an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit. The M-bit adder comprises M adder cells arranged in R rows, wherein a least significant adder cell in a first one of the rows of adder ce... | 08/04/2009 |
| 7523153 | Method of forcing 1's and inverting sum in an adder without incurring timing delay A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous car... | 04/21/2009 |
| 7509368 | Sparse tree adder circuit An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to pro... | 03/24/2009 |
| 7424508 | Self-timed carry look-ahead adder and summation method thereof A carry look-ahead adder may include: a carry generation circuit to generate carry propagation bit values and carry kill bit values for M blocks based on an N-bit addend and augend; a block carry circuit to generate block carry signals based upon the bit values; a M... | 09/09/2008 |
| 7330869 | Hybrid arithmetic logic unit Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: ... | 02/12/2008 |
| 7325025 | Look-ahead carry adder circuit A look-ahead carry adder circuit has multiple stages that are grouped into a carry generation blocks. The size of one of the carry generation blocks is three stages. There may be other carry generation blocks that are of a size that is a whole number multiple of thr... | 01/29/2008 |
| 7325024 | Adder circuit with sense-amplifier multiplexer front-end An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate... | 01/29/2008 |
| 7313585 | Multiplier circuit A multiplier circuit is disclosed for multiplying a multiplicand by a multiplier. The multiplier circuit includes a partial product generator and a partial product adder. The partial product generator includes a first input to receive a multiplicand; a second input ... | 12/25/2007 |
| 7277909 | High speed adder Provided is an adder composed of (N+1) circuit stages in the ease of 2.sup.N bits. In the case of N=4 (that is, 16 bits), provisional carries that indicate the case where carry is produced from a low order bit and the case where no carry is produced therefrom are ge... | 10/02/2007 |
| 7240085 | Faster shift value calculation using modified carry-lookahead adder Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input operands from three latches. A carry-lookahead adder receives the outpu... | 07/03/2007 |
| 7231414 | Apparatus and method for performing addition of PKG recoded numbers An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a fi... | 06/12/2007 |
| 7203714 | Logic circuit A CMOS logic circuit is disclosed wherein the number of kinds of basic parts is suppressed to five to allow designing of a circuit which operates at a high speed and repetitiveness of wiring lines is increased to allow designing of a circuit which is simple in circu... | 04/10/2007 |
| 7200629 | Apparatus and method for Fast Hadamard Transforms A Fast Hadamard Transform generator serially performs a Fast Hadamard Transform of a sampled signal from a first channel. The Fast Hadamard Transform generator comprises a series of stages. Each stage includes a shift register for serially receiving samples of the s... | 04/03/2007 |
| 7194501 | Complementary pass gate logic implementation of 64-bit arithmetic logic unit using propagate, generate, and kill An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folde... | 03/20/2007 |
| 7188134 | High-performance adder An adder for use in summing two binary numbers in an arithmetic logic unit of a processor. The adder includes a sparse carry-merge circuit adapted to generate a first predetermined number of carries and a plurality of intermediate carry generators coupled to the spa... | 03/06/2007 |
| 7159004 | Adder, multiplier and integrated circuit An adder includes a first XOR element for generating an XOR output of the first and the second data inputs, a first multiplexer for selecting one of the first carry input or the first data input while the XOR output is made a selection signal, a second multiplexer f... | 01/02/2007 |
| 7155601 | Multi-element operand sub-portion shuffle instruction execution An apparatus and method for performing a shuffle operation on packed data is described. In one embodiment, a 128-bit packed data operand having at eight data elements is accessed. In one embodiment, one of the data elements in the upper half of the data operand is s... | 12/26/2006 |
| 7139789 | Adder increment circuit In association with a circuit for adding binary numbers, it is often useful to increment the sum by a value of 1, for example on a conditional basis. Each of the combined adder and incrementer circuits embodying the invention also provides an output indicating wheth... | 11/21/2006 |
| 7124160 | Processing architecture having parallel arithmetic capability According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operand... | 10/17/2006 |
| 7085798 | Sense-amp based adder with source follower pass gate evaluation tree A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amp... | 08/01/2006 |
| 7076615 | Interval matching circuit for classification An efficient interval matching circuit configured with an input search-key terminal and an output terminal. The circuit generates a value on the output terminal that uniquely identifies all the intervals matching the input search-key. The circuit's memories are conf... | 07/11/2006 |
| 7007059 | Fast pipelined adder/subtractor using increment/decrement function with reduced register utilization A fast pipelined adder/subtractor using increment/decrement functions with reduced register utilization. Embodiments of the present invention replace double width registers with incrementor elements, pipelined single width registers, and pipelined carry bits. This i... | 02/28/2006 |
| 6930517 | Differential transistor and method therefor A differential transistor (10, 25) includes a depletion mode transistor (15,30) that has a source connected to a source of an enhancement mode transistor (11,26). The gates of the depletion mode and enhancement mode transistors are driven differ... | 08/16/2005 |
| 6839729 | Method and apparatus for a multi-purpose domino adder A method and apparatus for a multi-purpose adder is described. The method includes calculation of an initial sum for each corresponding N-bit portion of a received addend signal and a received augend signal. Generation of an initial carryout signal for each calculat... | 01/04/2005 |
| 6832235 | Multiple block adder using carry increment adder A multiple block adder is provided wherein carry select adder (CSA) is used in the most significant bit (MSB) block, a carry increment adder (CIA) is used in the least significant bit block and a combination of carry increment adder (CIA) and carry lookahead adder (... | 12/14/2004 |
| 6782406 | Fast CMOS adder with null-carry look-ahead A null-carry-lookahead adder is configured to generate and propagate a null-carry signal within and through blocks and groups of blocks within the adder. The null-carry signal terminates the effects of a carry input signal beyond the point at which the null-carry si... | 08/24/2004 |
| 6470374 | Carry look-ahead for bi-endian adder The inventive adder can perform carry look-ahead calculations for a bi-endian adder in a cache memory system. The adder can add one of +/-1, 4, 8, or 16 to a loaded value from memory, and the operation can be a 4 or 8 byte add. The inventive adder compris... | 10/22/2002 |
| 6408320 | Instruction set architecture with versatile adder carry control A data processing circuit has an adder unit divided into plural sections. Each section receives a subset of the bits of the operands and generates a subset of the bits of the resultant. A carry multiplexer is disposed between the sections. This carry mult... | 06/18/2002 |
| 6343306 | High speed one's complement adder A one's complement adder uses two two's complement adders, both of which are coupled to receive first and second addends at their addend inputs, however the first two's complement adder is adapted to output a first sum that is the one's complement sum tha... | 01/29/2002 |
| 6275839 | Method and system for immediate exponent normalization in a fast floating point adder A method and system for use in a data processing system is proposed, wherein the Input Exponent is used already in the subblocks of the mantissa addition. Early in the flow of a cycle, there are parts of the Potential exponent result generated and put tog... | 08/14/2001 |
| 6134576 | Parallel adder with independent odd and even sum bit generation cells A parallel adder is disclosed. The parallel adder includes a number of computational cells that operate to generate odd sum bits based on generate and propagate terms recursively computed and a plurality of carry-in bits. The parallel adder further includ... | 10/17/2000 |
| 6125381 | Recursively partitioned carry select adder A recursive divide and conquer strategy is applied to the structure of carry select adders. This adder is partitioned into two components, each computing the sums of their inputs with and without carry in, and each component is then recursively partitione... | 09/26/2000 |
| 6076098 | Adder for generating sum and sum plus one in parallel A circuit is disclosed herein which generates the sum of two numbers (A and B) and the sum plus 1 in parallel so as not to take any additional time to generate the sum plus 1 value. The circuit comprises a carry look-ahead (CLA) tree portion and a summer ... | 06/13/2000 |
| 6012079 | Conditional sum adder using pass-transistor logic and integrated circuit having the same Disclosed is an integrated pass-transistor logic circuit which includes a conditional sum adder. This sum adder has seven sum generation blocks of module form and two carry generation blocks. With the sum adder, before carry propagation which is generated... | 01/04/2000 |
| 6003059 | Carry select adder using two level selectors A carry select adder including a two level carry selector connected to multiple carry chains. Two or more adders produce at least two pairs of candidate carry-out signals in parallel. For each pair, a first candidate carry-out signal is based on a first p... | 12/14/1999 |
| 5975749 | Zero and one detection chain for a carry select adder A carry select adder includes an adder for outputting a first sum of values based on a first presumed carry-in of zero and a second sum of the values based on a second presumed carry-in of one. A sum unit produces an actual sum comprising either the first... | 11/02/1999 |
| 5953240 | SIMD TCP/UDP checksumming in a CPU A CPU adapted to calculate a checksum simultaneously on multiple values packed into a single register. An adder is provided which adds a number of values packed into a first register to a number of packed values from a second register. The adder is constr... | 09/14/1999 |
| 5944772 | Combined adder and logic unit A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the arithmetic and logic section of a microprocessor chip. The u... | 08/31/1999 |
| 5875125 | X+2X adder with multi-bit generate/propagate circuit The computation speed of a fast X+2X adder is improved by restructuring the carry generate/propagate logic. The adder is implemented with a multi-bit generation/propagation circuit which takes full advantage of the fact that in the X+2X computation, the i... | 02/23/1999 |
