Bizarre Patents
Nicotine Containing Dental Floss
Keep away cavities and cancer at the same time.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7653677 | Digital logic circuit for adding three binary words and method of implementing same A digital logic circuit includes at least one stage. Each stage includes sum logic, combinatorial logic, and carry chain logic. The sum logic is configured to generate a first sum signal from a first set of three input signals. The combinatorial logic includes a car... | 01/26/2010 |
| 7587444 | Data value addition A data processing apparatus for summing data values includes: a plurality of adder logic stages arranged in parallel; a control logic, in response to a request to sum two data values, to forward portions of the two data values to respective ones of the plurality of ... | 09/08/2009 |
| 7324540 | Network protocol off-load engines The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines). ... | 01/29/2008 |
| 7305516 | Multi-port memory device with precharge control There is provided a multi-port memory device, which is capable of preventing a first high data fail phenomenon at an initial operation in a current sensing type global data bus transmission/reception structure without causing a problem in a low data transmission. In... | 12/04/2007 |
| 7293056 | Variable width, at least six-way addition/accumulation instructions The present invention relates to a method and system for providing a variable width, at least six-way addition instruction in a processor. The method includes decoding an instruction as a variable width, at least six-way addition instruction, where the variable widt... | 11/06/2007 |
| 7266581 | Arithmetic circuit There is provided an arithmetic circuit for minimizing the delay of data path from the input of data to be operated to the output of the result of operation of data. To that end, the arithmetic circuit comprises a first selector to which one input data and a fixed d... | 09/04/2007 |
| 7260595 | Logic circuit and method for carry and sum generation and method of designing such a logic circuit Logic circuit for generating carry or sum bit output by combining binary inputs, includes bit level carry generate and propagate function logic receiving binary inputs and generating bit level carry generate/propagate function bits for binary inputs by respectively ... | 08/21/2007 |
| 7231414 | Apparatus and method for performing addition of PKG recoded numbers An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a fi... | 06/12/2007 |
| 7191205 | Function block A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from ... | 03/13/2007 |
| 7155601 | Multi-element operand sub-portion shuffle instruction execution An apparatus and method for performing a shuffle operation on packed data is described. In one embodiment, a 128-bit packed data operand having at eight data elements is accessed. In one embodiment, one of the data elements in the upper half of the data operand is s... | 12/26/2006 |
| 7149768 | 3-input arithmetic logic unit A 3-input adder/subtractor unit, having a first input for receiving a first operand A, a second input for receiving a second operand B, and a third input for receiving a third operand C. An add/subtract unit includes a control input for receiving a user-specified op... | 12/12/2006 |
| 7139788 | Multiplication logic circuit A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length col... | 11/21/2006 |
| 7124162 | Adder tree structure digital signal processor system and method A Wallace tree structure such as that used in a digital signal processor (DSP) is arranged to sum vectors. The structure has a number of adder stages, each of which may have half adders with two input nodes, and full adders with three input nodes. The structure is d... | 10/17/2006 |
| 7111033 | Carry save adders A carry save adder circuit for reducing the number of inputs to a lower number of outputs, the carry save adder circuit including four carry save adders, the four carry save adders being arranged in two layers with the first and second carry save adders being arrang... | 09/19/2006 |
| 7085797 | Addition circuit for accumulating redundant binary numbers An addition circuit for producing a sum of four redundant binary numbers includes a 4:2 compression adder for receiving each of the operand fields of the four redundant binary numbers, and producing a first sum field and a first carry field therefrom. The addition c... | 08/01/2006 |
| 7051062 | Apparatus and method for adding multiple-bit binary-strings Apparatus for determining a value, a sign and an overflow status of an addition of at least three n-bit data inputs. The apparatus comprising: a first adder, for adding the at least three n-bit data inputs, to provide a first output having at least 2n bits; a second... | 05/23/2006 |
| 7028066 | Vector SIMD processor A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An o... | 04/11/2006 |
| 7024414 | Storage of row-column data Table data is stored by parsing the table data into columns of values, formatting each column into a data stream, and transferring each data stream to a storage device for storage as a continuous strip of data. The strip of data is stored as a file that is not struc... | 04/04/2006 |
| 7002493 | Boolean logic tree reduction circuit A method and apparatus are provided for performing a Boolean logic tree function on all bits of a multiple-bit binary input data word having a plurality of bit positions. Each bit has one of first and second complementary logic states. A modified data word is formed... | 02/21/2006 |
| 6978290 | Carry ripple adder A carry ripple adder contains five first inputs for accepting five input bits having equal significance w that are to be summed and two second inputs for accepting two carry bits having the significance w. It also contains an output for a sum bit having the signific... | 12/20/2005 |
| 6959317 | Method and apparatus for increasing processing performance of pipelined averaging filters A pipelined processor such as an averaging filter including at least one subtractor section and at least one adder section. Both of the subtractor section and the adder section have a plurality of adder logic units. In comparison to the conventional processor, the p... | 10/25/2005 |
| 6954773 | Providing an adder with a conversion circuit in a slack propagation path In one embodiment of the present invention, a high-speed adder is provided. This adder may incorporate a conversion circuit in a slack propagation timing path to provide for improved performance. The present invention may be incorporated into single or multi-bit add... | 10/11/2005 |
| 6938061 | Parallel counter and a multiplication logic circuit A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinatins of each bit of a binary... | 08/30/2005 |
| 6925480 | Microarchitecture of an arithmetic unit The microarchitecture of the arithmetic unit includes two cascaded N bit adders to provide an N bits result in an accumulator. The arithmetic unit also includes a carry save adder, followed by an adder, which, along with the accumulator, are extended to N+1 bits. A ... | 08/02/2005 |
| 6865590 | Three input variable subfield comparation for fast matching The relationship between a sum of applied address operands and a matching virtual page number is exploited to minimize the adder size required for fast number comparison. In one embodiment, variably-sized addresses are accommodated by augmenting a portion of the app... | 03/08/2005 |
| 6832234 | In-place associative processor arithmetic A method of performing in-place arithmetic, particularly addition and subtraction, on numbers stored in respective consecutive rows of an array processor that has two tags registers. In a first machine cycle per bit, results of logical operations are stored in the t... | 12/14/2004 |
| 6820109 | System and method for predictive comparator following addition A computing system includes a plurality of full adders that each receives a bit-wise inversion of a bit of a first data, a bit of a second data, and a bit of a third data, respectively, and provides a sum output and a carry output. An exclusive-OR logic module recei... | 11/16/2004 |
| 6757703 | Associative processor addition and subtraction Methods of adding and subtracting sets of binary numbers using an associative processor. The inner loop over corresponding bits of the operands is executed in only three machine cycles. Only the carry bit of each loop iteration is carried forward to the next loop it... | 06/29/2004 |
| 6748411 | Hierarchical carry-select multiple-input split adder An adder or an integrated circuit including an adder, includes a hierarchical carry-select split adder capable of operating in a split mode of operation when a mode select input takes on a first state. It is also capable of operating in a hierarchical carry-select m... | 06/08/2004 |
| 6729168 | Circuit for determining the number of logical one values on a data bus There is disclosed a circuit for determining the number of Logic 1 bits in a group of N data bits. The circuit comprises: 1) an input stage of 4:3 carry-save adders, each of the 4:3 carry-save adders receiving four of the N data bits on four input lines and generati... | 05/04/2004 |
| 6701339 | Pipelined compressor circuit A pipelined four-to-two compressor includes sequential elements with embedded logic. One sequential element is a flip flop with complementary outputs that includes a master stage with embedded logic, a sensing stage, and one or more slave stages. The flip... | 03/02/2004 |
| 6584485 | 4 to 2 adder A four-input to two-output adder is disclosed. The four-input/two-output adder includes a sum-lookahead full adder and a modified full adder. The sum-lookahead full adder includes an XOR3 block and an AXOR block for receiving a first input, a second input... | 06/24/2003 |
| 6578063 | 5-to-2 binary adder A five-input/two-output binary adder is disclosed. The five-input/two-output adder includes five inputs and two outputs. Four levels of XOR logic gates are coupled between the five inputs and the two outputs for combining values received at the five input... | 06/10/2003 |
| 6549927 | Circuit and method for summing multiple binary vectors A method and circuit for summing multiples vectors is disclosed. The method includes receiving a set of input vectors and generating a set of decoded summation vectors. Each of the set of decoded summation vectors indicates the value of at least a portion... | 04/15/2003 |
| 6539061 | Efficient method for decompressing difference coded signals A data processing system for the compression and decompression of data using Differential Pulse Code Modulation, and optimized for fast execution using a parallel processing DSP such as the Texas Instruments TMS320C8X family. Decompression is speeded up o... | 03/25/2003 |
| 6519621 | Arithmetic circuit for accumulative operation An improved arithmetic circuit for accumulative operation for use in digital signal processors, microprocessors and so forth is described, in which the pipelined control becomes effective during accumulative operation by eliminating idling stages in the p... | 02/11/2003 |
| 6449629 | Three input split-adder An integrated circuit includes an adder having a first adder circuit for receiving a portion of the operands to be summed, along with corresponding carry-in inputs. The first adder circuit provides a sum output and carry-out outputs. A second adder circui... | 09/10/2002 |
| 6446107 | Circuitry for performing operations on binary numbers Circuitry for adding a first binary number (A) having a plurality of bits (a0, a1, . . . ) to a second binary number (B) having a plurality of bits (b0, b1, . . . ) to produce a third binary number (A+B) having ... | 09/03/2002 |
| 6411980 | Data split parallel shifter and parallel adder/subtractor Shift of input data without split by a shifter, generation of code extension data by a code extension data generator, and generation of a mask signal by a mask signal generator are carried out in parallel. The mask signal generator generates the mask sign... | 06/25/2002 |
| 6405298 | Linear address generator and method for generating a linear address using parallel computations and a single cycle algorithm A high-speed linear address generator (LAGEN) and method for generating a linear address are disclosed, which generator is operable to generate a linear address very quickly. In a preferred embodiment, the LAGEN has a parallel design, rather than a serial... | 06/11/2002 |
