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Pizza Pie With Concentric Rings of Crust
A pizza mold for forming a plurality of concentric raised ridges of dough (i.e., crust) on the surface of a pizza pie.
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| Number | Title | Issue Date |
| 7870182 | Digital signal processing circuit having an adder circuit with carry-outs An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first... | 01/11/2011 |
| 7840630 | Arithmetic logic unit circuit An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for... | 11/23/2010 |
| 7827226 | Hybrid arithmetic logic unit Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: ... | 11/02/2010 |
| 7720902 | Methods and apparatus for providing a reduction array Methods and apparatus provide for accumulating bit streams from four partial products and producing a carry-save output pair, including: producing the save, S, portion of the carry-save output pair, in accordance with the following Boolean expression: S=d3 XO... | 05/18/2010 |
| 7620677 | 4:2 Carry save adder and 4:2 carry save adding method Provided are a simplified 4:2 carry save adder (CSA) cell and a 4:2 carry save adding method. The 4:2 CSA cell is formed of an odd detector and first through sixth switches through logic optimization. The odd detector generates an XOR of the first through fourth inp... | 11/17/2009 |
| 7487198 | Multibit bit adder The invention relates to an adder for adding at least four bits of the same significance w, said adder having a first number of inputs for receiving the bits of the same significance w that are to be added and a number of outputs, the bits to be added being applied ... | 02/03/2009 |
| 7444366 | Faster shift value calculation using modified carry-lookahead adder Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input operands from three latches. A carry-lookahead adder receives the outpu... | 10/28/2008 |
| 7430293 | Cryptographic device employing parallel processing A cryptography processor includes a central processing unit and a co-processor, the co-processor comprising a plurality of calculating subunits as well as a single control unit which is coupled to each of the plurality of calculating subunits. A cryptographic operat... | 09/30/2008 |
| 7392277 | Cascaded domino four-to-two reducer circuit and method A cascaded differential domino four-to-two reducer. In an embodiment, the four-to-two reducer is constructed of a first three-to-two reducer and a second three-to-two reducer directly connected to the first three-to-two reducer. In a further embodiment, the first an... | 06/24/2008 |
| 7352131 | Electric lamp comprising a lead-free glass component The electric lamp has a glass component with a composition which, according to the invention, is substantially free of PbO and has the following constituents: 55–70 wt. % SiO2, | 04/01/2008 |
| 7330869 | Hybrid arithmetic logic unit Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: ... | 02/12/2008 |
| 7302460 | Arrangement of 3-input LUT's to implement 4:2 compressors for multiple operand arithmetic A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB is configured to determine a compression of a plurality of N-bit numbers. The LAB includes look-up table (LUT) logic cells.... | 11/27/2007 |
| 7284029 | 4-to-2 carry save adder using limited switching dynamic logic A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry s... | 10/16/2007 |
| 7275048 | Product support of computer-related products using intelligent agents An apparatus, program product, and method utilize a dynamic, automated, extensible and flexible intelligent agent-based product support “framework” to facilitate the provision of product support services to customers of computer-related products. Agent platforms... | 09/25/2007 |
| 7272624 | Fused booth encoder multiplexer A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results... | 09/18/2007 |
| 7216141 | Computing carry-in bit to most significant bit carry save adder in current stage A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the ... | 05/08/2007 |
| 7191205 | Function block A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from ... | 03/13/2007 |
| 7159003 | Method and apparatus for generating sign-digit format of sum of two numbers A system and method for converting two binary digits into redundant sign-digit format. The system comprises a first adder for adding the binary digits together to generate a first result. A second adder adds an input carry from a previous digit to the first result a... | 01/02/2007 |
| 7124162 | Adder tree structure digital signal processor system and method A Wallace tree structure such as that used in a digital signal processor (DSP) is arranged to sum vectors. The structure has a number of adder stages, each of which may have half adders with two input nodes, and full adders with three input nodes. The structure is d... | 10/17/2006 |
| 7120858 | Method and device for off-loading message digest calculations A method and device for off-loading from an application program the calculation of a data-integrity-checking value for specified data in a computer system. The data may be included in a message together with the integrity-checking value or may be in a portion of a m... | 10/10/2006 |
| 7111033 | Carry save adders A carry save adder circuit for reducing the number of inputs to a lower number of outputs, the carry save adder circuit including four carry save adders, the four carry save adders being arranged in two layers with the first and second carry save adders being arrang... | 09/19/2006 |
| 7089360 | Shared cache wordline decoder for redundant and regular addresses In one embodiment, a wordline decoder provides access to cache memory locations when addresses are bypassed directly from arithmetic circuitry in redundant form. The wordline decoder is also designed to provide access to cache memory locations when addresses are rec... | 08/08/2006 |
| 7085797 | Addition circuit for accumulating redundant binary numbers An addition circuit for producing a sum of four redundant binary numbers includes a 4:2 compression adder for receiving each of the operand fields of the four redundant binary numbers, and producing a first sum field and a first carry field therefrom. The addition c... | 08/01/2006 |
| 7051062 | Apparatus and method for adding multiple-bit binary-strings Apparatus for determining a value, a sign and an overflow status of an addition of at least three n-bit data inputs. The apparatus comprising: a first adder, for adding the at least three n-bit data inputs, to provide a first output having at least 2n bits; a second... | 05/23/2006 |
| 7039667 | 4-2 compressor A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a f... | 05/02/2006 |
| 7035893 | 4-2 Compressor A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a f... | 04/25/2006 |
| 7035331 | Method and apparatus for performing a pixel averaging instruction In an embodiment, a functional unit including a compressor section and a 36-bit SIMD adder is used to perform a STMD four-pixel averaging instruction. The functional unit generates four four-pixel averages. Four pixel values and a rounding value are compressed into ... | 04/25/2006 |
| 7028066 | Vector SIMD processor A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An o... | 04/11/2006 |
| 7007053 | Area efficient realization of coefficient architecture for bit-serial FIR, IIR filters and combinational/sequential logic structure with zero latency clock output An area-efficient realization of a coefficient block includes hardware sharing techniques and optimizations applied to this block. The block is connected to coefficient lines coming from a delay block to be connected to perform a filtering operation or a mathematica... | 02/28/2006 |
| 6989843 | Graphics system with an improved filtering adder tree A sample-to-pixel calculation unit in a graphics system may comprise an adder tree. The adder tree includes a plurality of adder cells coupled in a tree configuration. Input values are presented to a first layer of adder cells. Each input value may have two associat... | 01/24/2006 |
| 6918024 | Address generating circuit and selection judging circuit An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the... | 07/12/2005 |
| 6785703 | Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technology An adder circuit is provided that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that various levels of both N-type devices and P-type devices are both “on” at the same when that leg is to be open. The logic is then d... | 08/31/2004 |
| 6754689 | Method and apparatus for performing subtraction in redundant form arithmetic A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in redundant form to subtract numbers received in redundant form, including numbers received from a bypass circuit. The method includes generating a complemented redun... | 06/22/2004 |
| 6742011 | Apparatus and method for increasing performance of multipliers utilizing regular summation circuitry The present invention generally relates to an apparatus and method for efficiently summing the partial product bits produced by a multiplier. Briefly described, in architecture, the apparatus includes a first array of odd/even summation circuitry, a second array of ... | 05/25/2004 |
| 6732136 | Differential, low voltage swing reducer A small swing reducer circuit. An apparatus includes a first number of input terminals including at least two input terminals coupled to receive a differential small swing signal and a reducer circuit to generate differential, small swing sum and carry output signal... | 05/04/2004 |
| 6711633 | 4:2 compressor circuit for use in an arithmetic unit A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first interm... | 03/23/2004 |
| 6584485 | 4 to 2 adder A four-input to two-output adder is disclosed. The four-input/two-output adder includes a sum-lookahead full adder and a modified full adder. The sum-lookahead full adder includes an XOR3 block and an AXOR block for receiving a first input, a second input... | 06/24/2003 |
| 6578063 | 5-to-2 binary adder A five-input/two-output binary adder is disclosed. The five-input/two-output adder includes five inputs and two outputs. Four levels of XOR logic gates are coupled between the five inputs and the two outputs for combining values received at the five input... | 06/10/2003 |
| 6567835 | Method and apparatus for a 5:2 carry-save-adder (CSA) The present invention is a 5:2 carry-save-adder (CSA) that receives the five input signals I0, I1, I2, I3 and I4 and computes the two output signals SUM and CARRY. The 5:2 CSA comprises a first level of logic circuitry and a second level of logic circuitr... | 05/20/2003 |
| 6405298 | Linear address generator and method for generating a linear address using parallel computations and a single cycle algorithm A high-speed linear address generator (LAGEN) and method for generating a linear address are disclosed, which generator is operable to generate a linear address very quickly. In a preferred embodiment, the LAGEN has a parallel design, rather than a serial... | 06/11/2002 |
