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| Number | Title | Issue Date |
| 7734675 | System and method for generating a binary result in a data processing environment A method for processing data includes generating one or more binary results based on one or more inputs and receiving one or more of the binary results. One or more conditional carryout signals may then be generated based on one or more of the binary results. The me... | 06/08/2010 |
| 7689643 | N-bit constant adder/subtractor An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic... | 03/30/2010 |
| 7562107 | Mixed-type adder comprising multiple sub-adders having different carry propagation schemes Disclosed is a mixed-type adder with optimized design costs. The mixed-type adder includes I sub adders, (where, I is a positive number larger than 1). An overall bit width of the mixed-type adder is divided into I bit groups which are respectively allocated to the ... | 07/14/2009 |
| 7430293 | Cryptographic device employing parallel processing A cryptography processor includes a central processing unit and a co-processor, the co-processor comprising a plurality of calculating subunits as well as a single control unit which is coupled to each of the plurality of calculating subunits. A cryptographic operat... | 09/30/2008 |
| 7325024 | Adder circuit with sense-amplifier multiplexer front-end An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate... | 01/29/2008 |
| 7302460 | Arrangement of 3-input LUT's to implement 4:2 compressors for multiple operand arithmetic A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB is configured to determine a compression of a plurality of N-bit numbers. The LAB includes look-up table (LUT) logic cells.... | 11/27/2007 |
| 7290026 | Low-power high-speed 4-2 compressor with minimized transistor count A circuit for use in a microprocessor, comprising a 4-2 compressor circuit having a full adder formed of dual XOR/XNOR cells and a 2-1 MUX. The full adder uses minimum sized XOR/XNOR cells. ... | 10/30/2007 |
| 7266581 | Arithmetic circuit There is provided an arithmetic circuit for minimizing the delay of data path from the input of data to be operated to the output of the result of operation of data. To that end, the arithmetic circuit comprises a first selector to which one input data and a fixed d... | 09/04/2007 |
| 7218138 | Efficient implementations of the threshold-2 function A circuit and a method for operating the circuit are disclosed. A first step of the method generally comprises generating a plurality of first intermediate signals in two parallel first operations each responsive to a respective half of a plurality of input signals.... | 05/15/2007 |
| 7159003 | Method and apparatus for generating sign-digit format of sum of two numbers A system and method for converting two binary digits into redundant sign-digit format. The system comprises a first adder for adding the binary digits together to generate a first result. A second adder adds an input carry from a previous digit to the first result a... | 01/02/2007 |
| 7155601 | Multi-element operand sub-portion shuffle instruction execution An apparatus and method for performing a shuffle operation on packed data is described. In one embodiment, a 128-bit packed data operand having at eight data elements is accessed. In one embodiment, one of the data elements in the upper half of the data operand is s... | 12/26/2006 |
| 7124162 | Adder tree structure digital signal processor system and method A Wallace tree structure such as that used in a digital signal processor (DSP) is arranged to sum vectors. The structure has a number of adder stages, each of which may have half adders with two input nodes, and full adders with three input nodes. The structure is d... | 10/17/2006 |
| 7124160 | Processing architecture having parallel arithmetic capability According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operand... | 10/17/2006 |
| 7120894 | Pass-transistor logic circuit and a method of designing thereof A method of designing a logic circuit including pass transistors is disclosed. A logic group having a complementary variable in a given logical expression to be realized into the logic circuit is mapped using a multiplexer composed of a combination of the pass trans... | 10/10/2006 |
| 7089277 | Computation circuit having dynamic range extension function A computation circuit which can obtain n+m-digit accumulation results by using an n-digit computation unit. This computation circuit comprises a computation unit which performs additions of n-digit data; an m-digit up/down counter; and a control circuit which uses t... | 08/08/2006 |
| 7058678 | Fast forwarding ALU An apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit is described. The apparatus and method operating on a first binary number and a second binary number comprise: a first arithmetic logic unit (ALU) operating... | 06/06/2006 |
| 7051296 | Method and apparatus for parallel carry chains An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output... | 05/23/2006 |
| 7024446 | Circuitry for arithmetically accumulating a succession of arithmetic values A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the u... | 04/04/2006 |
| 7007059 | Fast pipelined adder/subtractor using increment/decrement function with reduced register utilization A fast pipelined adder/subtractor using increment/decrement functions with reduced register utilization. Embodiments of the present invention replace double width registers with incrementor elements, pipelined single width registers, and pipelined carry bits. This i... | 02/28/2006 |
| 6990509 | Ultra low power adder with sum synchronization An ultra low power adder with sum synchronization which provides a power reduction method in the binary carry propagate adders by using a carry skip technique. The invention eliminates glitches at the adder outputs by preventing signal transitions at the sum outputs... | 01/24/2006 |
| 6970899 | Calculating unit and method for subtracting Calculating unit having adder blocks, each having single adders, a carry input, a carry output, and a carry pass output, wherein a signal at the carry pass output is indicative of a carry passing through the adder block. Depending on the carry pass output signal, a ... | 11/29/2005 |
| 6970994 | Executing partial-width packed data instructions A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectur... | 11/29/2005 |
| 6965910 | Calculating unit and method for adding A calculating unit comprises several adder blocks with single adders, a clock generator and control means. A carry pass means is associated with each adder block, which determines whether a carry passes fully through the respective adder block. If it is determined t... | 11/15/2005 |
| 6959317 | Method and apparatus for increasing processing performance of pipelined averaging filters A pipelined processor such as an averaging filter including at least one subtractor section and at least one adder section. Both of the subtractor section and the adder section have a plurality of adder logic units. In comparison to the conventional processor, the p... | 10/25/2005 |
| 6938061 | Parallel counter and a multiplication logic circuit A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinatins of each bit of a binary... | 08/30/2005 |
| 6934733 | Optimization of adder based circuit architecture An adder based circuit embodied in an integrated circuit includes an input module, a carry module and an output module. The carry module has a minimum depth defined by a recursive expansion of at least one function associated with the carry module based on a variabl... | 08/23/2005 |
| 6925553 | Staggering execution of a single packed data instruction using the same circuit A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, ... | 08/02/2005 |
| 6912560 | Adder with improved overflow flag generation An adder includes a number of computational stages each associated with one or more bit positions. Particular ones of the computational stages generate a sum output signal and a primary carry-output signal of the adder. A flag generation circuit is coupled to at lea... | 06/28/2005 |
| 6807556 | Method and apparatus for parallel carry chains An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output... | 10/19/2004 |
| 6735612 | Carry skip adder A carry skip adder has a plurality of ripple adders, in which at least one part of the plurality of ripple adders is divided into a plurality of groups, and a carry signal is transferred from one group to one upper group. In addition, a circuit for calculating C=C | 05/11/2004 |
| 6681236 | Method of performing operations with a variable arithmetic The process for performing operations with a variable arithmetic does not call for any shifting of the data in the different registers that come into play in the operation. The input registers can have empty parts which are completed by appropriate bit se... | 01/20/2004 |
| 6584484 | Incorporation of split-adder logic within a carry-skip adder without additional propagation delay An n-bit carry-skip adder includes a number of carry-skip stages and a logic circuit associated with one or more of the stages. The logic circuit includes split-adder logic and carry-skip logic configured such that a split control signal associated with t... | 06/24/2003 |
| 6523057 | High-speed digital accumulator with wide dynamic range A high-speed, wide dynamic range, digital accumulator includes a first adder stage in which an input addend is added to a value of a least significant part of an output of an accumulator from a preceding clock period. The accumulator also includes at leas... | 02/18/2003 |
| 6502120 | Adder circuit employing logic gates having discrete weighted inputs and a method of operation therewith A circuit and method for deriving an adder output bit from adder input bits. In one embodiment, the circuit includes: (1) first, second and third threshold logic gates that generate intermediate bits based on threshold comparisons of concatenations of one... | 12/31/2002 |
| 6489900 | Bus encoding/decoding apparatus and method A bus encoding/decoding apparatus and method for a low power digital signal processor (DSP), which uses a narrow data bus, is provided. The apparatus for encoding n bits of data of a data bus, includes a conditional inverting unit for inverting each of (n... | 12/03/2002 |
| 6408320 | Instruction set architecture with versatile adder carry control A data processing circuit has an adder unit divided into plural sections. Each section receives a subset of the bits of the operands and generates a subset of the bits of the resultant. A carry multiplexer is disposed between the sections. This carry mult... | 06/18/2002 |
| 6263424 | Execution of data dependent arithmetic instructions in multi-pipeline processors A single chip microprocessor has at least two parallel pipelines that each have multiple processing stages, one of which is an instruction execution stage with a full functioned arithmetic logic unit (ALU). The ALU of one pipeline includes an adder that h... | 07/17/2001 |
| 6260055 | Data split parallel shifter and parallel adder/subtractor Shift of input data without split by a shifter, generation of code extension data by a code extension data generator, and generation of a mask signal by a mask signal generator are carried out in parallel. The mask signal generator generates the mask sign... | 07/10/2001 |
| 6199091 | Carry skip adder A carry skip adder comprises a plurality of ripple adders, wherein at least one part of the plurality of ripple adders is divided into a plurality of groups, and a carry signal is transferred from one group to one upper group. In addition, a circuit for c... | 03/06/2001 |
| 6141675 | Method and apparatus for custom operations Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time multimedia capabilities while maintaining advantages of a special... | 10/31/2000 |
