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...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 7693930 | Asynchronous full adder, asynchronous microprocessor and electronic apparatus An asynchronous adder permits asynchronous design in which dual-rail encoding is employed, not only for a control part but also for a datapath part including an ALU. An asynchronous adder of an exemplary embodiment includes a combinational circuit to perform full ad... | 04/06/2010 |
| 7392277 | Cascaded domino four-to-two reducer circuit and method A cascaded differential domino four-to-two reducer. In an embodiment, the four-to-two reducer is constructed of a first three-to-two reducer and a second three-to-two reducer directly connected to the first three-to-two reducer. In a further embodiment, the first an... | 06/24/2008 |
| 6571269 | Noise-tolerant digital adder circuit and method A digital adder circuit is implemented using a Kogge-Stone architecture. Various embodiments utilize single-ended domino circuits, to which are input single-ended primary addends. Dual-function generator circuits generate differential sum and sum-compleme... | 05/27/2003 |
| 6567836 | Multi-level carry-skip adder Circuits for binary adders to efficiently skip a carry bit over two or more bit positions with two or more carry-skip paths. In one implementation, such a binary adder includes a network of carry-processing cells for producing kill, generate, and propagat... | 05/20/2003 |
| 6466960 | Method and apparatus for performing a sum-and-compare operation A method and apparatus are provided for performing a fast sum-and-compare operation. The apparatus of the present invention utilizes a single carry save adder in conjunction with a zero detect circuit for performing logic operations to determine whether o... | 10/15/2002 |
| 5951631 | Carry lookahead adder A high-performance carry lookahead adder (CLA) which can reduce the delay time of the whole adder by constructing a carry generator used therein with NMOS logics, thereby effecting a high-speed operation of the adder along with a lower power-consumption. ... | 09/14/1999 |
| 5905667 | Full adder using NMOS transistor A full adder includes a static logic block for generating an inverted carry with respect to multiple inputs through an inverted carry output node; a first dynamic inverter logic block for inverting the inverted carry produced from the static logic block v... | 05/18/1999 |
| 5880968 | Method and apparatus for reducing power usage within a domino logic unit Power reduction is achieved either statically or dynamically within domino logic circuits. For static power reduction, representative input signals to the logic circuit are analyzed and any variation from purely random signals is detected. The domino circ... | 03/09/1999 |
| 5880986 | Method and apparatus for reducing power usage within a domino logic unit Power reduction is achieved either statically or dynamically within domino logic circuits. For static power reduction, representative input signals to the logic circuit are analyzed and any variation from purely random signals is detected. The domino circ... | 03/09/1999 |
| 5719803 | High speed addition using Ling's equations and dynamic CMOS logic The methods and apparatus disclosed allow for a direct implementation of Ling's equations in a dynamic CMOS logic environment. In summary, low order Ling pseudo-carries and group propagate terms are generated in parallel in a single gate delay. After gene... | 02/17/1998 |
| 5596520 | CMOS full adder circuit with pair of carry signal lines A full adder circuit has a plurality of full adders each provided for each bit. Each full adder has: a calculation block (31a) responsive to a first carry signal (C) given by a preceding stage bit as a differential signal and two external input data (A1, ... | 01/21/1997 |
| 5491653 | Differential carry-save adder and multiplier A Carry-Save Adder circuit having differential signal response and output is provided. The circuit includes a pair of cross-coupled transistors powered by an upper voltage rail. The output of a first transistor of the pair of cross-coupled transistors is ... | 02/13/1996 |
| 5406506 | Domino adder circuit having MOS transistors in the carry evaluating paths An improved Domino adder circuit has a carry evaluating logic, including a precharge transistor, an evaluation transistor, and three carry evaluating paths connected the precharge and evaluation transistors, and constituted by five N-channel Metal Oxide S... | 04/11/1995 |
| 5357456 | Arithmetic circuit An arithmetic circuit for addition or subtraction includes a carry or borrow signal control section which includes a transfer gate having N-ch and P-ch transistors for transferring an input carry- or borrow-in as an output carry- or borrow-out. A signal t... | 10/18/1994 |
| 5329477 | Adder circuit having carry signal initializing circuit Disclosed herein is an adder which comprises a Manchester-type adder circuit and which can operate as fast as a dynamic adder, and can perform addition during the clock cycle as a static dynamic adder. Hence, the adder serves to increase the operating fre... | 07/12/1994 |
| 5095458 | Radix 4 carry lookahead tree and redundant cell therefor A high radix carry lookahead tree includes a plurality of tree nodes, each of the tree nodes including a carrying chain or a variation thereof, and/or a NAND gate chain or a variation thereof; and each tree node may have three or more children.... | 03/10/1992 |
| 4899305 | Manchester carry adder circuit A 16-bit adder architecture configured uniquely as two 8-bit adders. The first 8-bit adder uses a static technique to perform addition of the least significant bits and a dynamic technique to perform addition on the remaining bits. The second 8-bit adder ... | 02/06/1990 |
| 4885716 | High speed carry chain A carry chain includes a plurality of carry latches (20') which are disposed along a carry propagating line (12) to propagate a carry signal to a latch node (18). During precharge of the latch node (18), a precharge transistor (26') pulls the node to a lo... | 12/05/1989 |
| 4858167 | Parallel binary adder having grouped stages including dynamic logic to increase carry propagation speed A binary adder circuit is described using dynamic transistor logic in which for high speed carry propagation the adder stages are grouped in pairs or larger numbers and additional dynamic logic means is provided in each group to control a single transisto... | 08/15/1989 |
| 4807176 | Manchester type carry propagation circuit A Manchester type carry propagation circuit of this invention has a precharge clock signal (24) applied to the gate of an NMOS transistor (23) having a high threshold, to precharge a carry signal line (22) to an intermediate potential. When a carry signal... | 02/21/1989 |
| 4805130 | Arithmetic and logic circuit stage A circuit for performing operations on two bits (A,B), including the processing of a carry from a preceding circuit (CIN) and transmitting it to a subsequent circuit (COUT). The circuit includes a network which is formed by MOS transistors which can be pr... | 02/14/1989 |
| 4802112 | MOS transistor circuit When a carry signal generated in an n-th bit is propagated to an (n+1)th bit, two n-MOS transistors (12n+1 and 13n+1) connected by a signal line (Cn) are turned on to prompt transition of the signal line (Cn) to... | 01/31/1989 |
| 4718034 | Carry-save propagate adder A carry-save propagate adder employing two exclusive-OR blocks, a multiplexer block for selecting between a carry propagate input or a carry-save input, and a further multiplexer block for supplying as a carry-save output either the carry-save input or on... | 01/05/1988 |
| 4677584 | Data processing system with an arithmetic logic unit having improved carry look ahead A data processing system has an arithmetic logic unit that includes a plurality of summation units for summing an ADDEND with a AUGEND to obtain a first signal that represents the summation of the ADDEND, AUGEND and a CARRY IN. Each summation units also p... | 06/30/1987 |
| 4559608 | Arithmetic logic unit An ALU having improved propagate and generate signal section as well as carry and sum logic section to decrease the propagation delays. The propagate and generate signal section is specifically designed to be used with a dual ported RAM such that transiti... | 12/17/1985 |
| 4054788 | Modular binary half-adder Half-adder logic modules employing separate summing and carry circuitry are used in the construction of a modular binary half-adder. Carry bits of less significant digits are calculated independent of and prior to the calculation of corresponding sum bits... | 10/18/1977 |
