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| Number | Title | Issue Date |
| 8135768 | Adder with reduced capacitance An electronic circuit for performing logic operations is provided. The electronic circuit comprises a logic gate having at least two binary inputs adapted to receive corresponding input binary digits; an output for outputting an output signal; signal transmission me... | 03/13/2012 |
| 7428568 | Symmetric cascaded domino carry generate circuit A symmetric differential domino carry generate gate. In an embodiment, the load for the true inputs is equal to the load for the compliment inputs. In another embodiment, the output drive strength for the true output is the same as the output drive strength for the ... | 09/23/2008 |
| 7415245 | Pulse shaping signals for ultrawideband communication An ultrawideband radio frequency pulse is generated by shaping a carrier signal having a selected frequency with a window function. The shaped carrier is gated to produce the ultrawideband pulse. In further embodiments, the window function comprises a sinusoidal fun... | 08/19/2008 |
| 7290026 | Low-power high-speed 4-2 compressor with minimized transistor count A circuit for use in a microprocessor, comprising a 4-2 compressor circuit having a full adder formed of dual XOR/XNOR cells and a 2-1 MUX. The full adder uses minimum sized XOR/XNOR cells. ... | 10/30/2007 |
| 7228325 | Bypassable adder An adder for adding a signal at a first input (A) and a second input (B) to produce an adder output (S) is disclosed. The adder comprises a bypass input (bypass) and a logic circuit, communicatively coupled to the bypass input (bypass), the first input (A), and the ... | 06/05/2007 |
| 7206801 | Digital multiplier with reduced spurious switching by means of Latch Adders A digital Parallel Multiplier has a Partial Product Generator, a First Stage Adder Circuit and a Final Stage Adder Circuit. The spurious switching in the First Stage Adder Circuit may be substantially reduced by synchronizing the input signals to the Adders in First... | 04/17/2007 |
| 7203714 | Logic circuit A CMOS logic circuit is disclosed wherein the number of kinds of basic parts is suppressed to five to allow designing of a circuit which operates at a high speed and repetitiveness of wiring lines is increased to allow designing of a circuit which is simple in circu... | 04/10/2007 |
| 7191205 | Function block A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from ... | 03/13/2007 |
| 7190756 | Hybrid counter with an asynchronous front end Integrated circuit counting apparatuses are described. More particularly, a hybrid counter (203) including an asynchronous counter (310) front end and a synchronous counter (311) back end is described. The asynchronous counter (310) inclu... | 03/13/2007 |
| 7185042 | High speed, universal polarity full adder which consumes minimal power and minimal area A low power, high speed full adder cell is described. This cell supports all possible combinations of active high/active low input/output signal polarity (32 different combinations), without adding extra inverters or extra transistors. The cell makes liberal use of ... | 02/27/2007 |
| 7170317 | Sum bit generation circuit Sum bit generation circuit includes first logic generating first signal as XOR of first and second input signals and second signal as the inverse of XOR of the first and second input signals; second logic receiving the first and second signals generated by first log... | 01/30/2007 |
| 7155474 | Current-mode multi-valued full adder in semiconductor device A full adder in a semiconductor device, includes a reference current generation unit for generating a reference current, a carry generation unit for generating a threshold current for generating a carry in response to the reference current and for generating the car... | 12/26/2006 |
| 7126563 | Brightness correction apparatus and method for plasma display Brightness correction apparatus and method for a plasma display, where the non-linear relationship between the gray scale and the brightness of the plasma display is considered. The brightness error is measured to build up a brightness error table. When the gray sca... | 10/24/2006 |
| 7042245 | Low power consumption MIS semiconductor device A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the su... | 05/09/2006 |
| 7039667 | 4-2 compressor A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a f... | 05/02/2006 |
| 7035893 | 4-2 Compressor A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a f... | 04/25/2006 |
| 6954773 | Providing an adder with a conversion circuit in a slack propagation path In one embodiment of the present invention, a high-speed adder is provided. This adder may incorporate a conversion circuit in a slack propagation timing path to provide for improved performance. The present invention may be incorporated into single or multi-bit add... | 10/11/2005 |
| 6904447 | High speed low power 4-2 compressor A high speed low powered 4-2 compressor according to the present invention performs an XOR/XNOR operation of input data by using a single input type NAND/NOR logic circuit and a dual input type NAND/NOR logic circuit. Thus, delays to generate complementary signals a... | 06/07/2005 |
| 6785703 | Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technology An adder circuit is provided that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that various levels of both N-type devices and P-type devices are both “on” at the same when that leg is to be open. The logic is then d... | 08/31/2004 |
| 6658446 | Fast chainable carry look-ahead adder A chainable adder receives bits (A, B, C) to give complementary sum outputs (SO, SO*) and carry outputs (CO, CO*). A first stage has differential pairs (P1, P2, P3) receiving bits (A, B, C), respectively, and complements (A*, B*, C*), respectively. The pairs h... | 12/02/2003 |
| 6567836 | Multi-level carry-skip adder Circuits for binary adders to efficiently skip a carry bit over two or more bit positions with two or more carry-skip paths. In one implementation, such a binary adder includes a network of carry-processing cells for producing kill, generate, and propagat... | 05/20/2003 |
| 6480875 | Adder circuit and associated layout structure In an adder circuit, a block carry generation logic over three consecutive digits is produced from the following equations. G0=g2+p2.multidot.g1+p2.multidot.p1.multidot.g0 /g0=/p2+/g2.multidot./p1+/g2.multidot./g1.multidot./g0 In other words, the block carry genera... | 11/12/2002 |
| 6345286 | 6-to-3 carry-save adder A 6-to-3 carry-save binary adder is disclosed. The 6-to-3 carry-save adder includes a means for receiving six data inputs and a means for simultaneously adding the six data inputs to generate a first data output, a second data output, and a third data out... | 02/05/2002 |
| 6259275 | Logic gate having reduced power dissipation and method of operation thereof A circuit for, and method of, decreasing DC power dissipation in a logic gate and a processor incorporating the circuit or the method. In one embodiment, wherein the logic gate has at least two binary inputs adapted to receive corresponding input binary d... | 07/10/2001 |
| 6055557 | Adder circuit and method therefor An adder (300) generates encoded outputs to conserve power. In particular, the adder provides "B2" encoded outputs which only drive one bit per every two bits at a time on conductive lines in a data processing system. A binary input is encoded by an encod... | 04/25/2000 |
| 6003059 | Carry select adder using two level selectors A carry select adder including a two level carry selector connected to multiple carry chains. Two or more adders produce at least two pairs of candidate carry-out signals in parallel. For each pair, a first candidate carry-out signal is based on a first p... | 12/14/1999 |
| 5991789 | Circuit arrangement for realizing logic elements that can be represented by threshold value equations In a circuit arrangement wherein all logic elements can be represented in the form of a threshold value equation, for this purpose, transistors connected in parallel of a transistor unit are dimensioned in such a way that the cross-currents flowing throug... | 11/23/1999 |
| 5951631 | Carry lookahead adder A high-performance carry lookahead adder (CLA) which can reduce the delay time of the whole adder by constructing a carry generator used therein with NMOS logics, thereby effecting a high-speed operation of the adder along with a lower power-consumption. ... | 09/14/1999 |
| 5923205 | Semiconductor arithmetic circuit A semiconductor arithemetic circuit which performs calculation of an analog vector with a high accuracy at a high speed. A semiconductor arithemetic circuit having a plurality of MOS type transistors, wherein the source electrodes are connected to one ano... | 07/13/1999 |
| 5905667 | Full adder using NMOS transistor A full adder includes a static logic block for generating an inverted carry with respect to multiple inputs through an inverted carry output node; a first dynamic inverter logic block for inverting the inverted carry produced from the static logic block v... | 05/18/1999 |
| 5875124 | Full adder circuit A full adder that operates rapidly with low power supply voltage and minimal power consumption, and further, that occupies a small area on a semiconductor element. A sum signal calculation circuit 10 of full adder 1 performs addition of input signals A an... | 02/23/1999 |
| 5818747 | Small, fast CMOS 4-2 carry-save adder cell A CMOS 4-2 carry-save adder cell implementation. A XNOR gate is used in the computation of SUM and CARRY. By using an XNOR gate, there are no possible input permutations which will cause any output in the SUM logic to be driven by two P-channel devices in... | 10/06/1998 |
| 5761107 | Method and apparatus for improving the speed of a logic circuit The invention is disclosed as embodied in a data processing system circuit for outputting a signal based on an evaluation of input signals coupled to the circuit. The circuit has a number of transistors configured so that the output signal is triggered by... | 06/02/1998 |
| 5596520 | CMOS full adder circuit with pair of carry signal lines A full adder circuit has a plurality of full adders each provided for each bit. Each full adder has: a calculation block (31a) responsive to a first carry signal (C) given by a preceding stage bit as a differential signal and two external input data (A1, ... | 01/21/1997 |
| 5491653 | Differential carry-save adder and multiplier A Carry-Save Adder circuit having differential signal response and output is provided. The circuit includes a pair of cross-coupled transistors powered by an upper voltage rail. The output of a first transistor of the pair of cross-coupled transistors is ... | 02/13/1996 |
| 5406506 | Domino adder circuit having MOS transistors in the carry evaluating paths An improved Domino adder circuit has a carry evaluating logic, including a precharge transistor, an evaluation transistor, and three carry evaluating paths connected the precharge and evaluation transistors, and constituted by five N-channel Metal Oxide S... | 04/11/1995 |
| 5357456 | Arithmetic circuit An arithmetic circuit for addition or subtraction includes a carry or borrow signal control section which includes a transfer gate having N-ch and P-ch transistors for transferring an input carry- or borrow-in as an output carry- or borrow-out. A signal t... | 10/18/1994 |
| 5343418 | Three-to-two carry save adder cell A three-to-two adder which takes advantage of the fact that one of the inputs lags behind the other two inputs. A gate delay is eliminated in the currently preferred embodiment, an output is provided within two gate delays from the time that the last to a... | 08/30/1994 |
| 5265044 | High speed arithmetic and logic generator with reduced complexity using negative resistance A technique for generating a carry, AND, OR, NAND, NOR, INVERTING logic and sum and carry: operation in a one or at most two device delay by employing negative differential resistance devices. Circuits implemented with this technique are not only extremel... | 11/23/1993 |
| 5233233 | Multiplexer for use in a full adder having different gate delays The semiconductor integrated circuit device includes a select gate for selectively transmitting a signal. The select gate includes a first gate for receiving and transferring a first logic signal to an output node, and a second gate for receiving and tran... | 08/03/1993 |
