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| Number | Title | Issue Date |
| 4878190 | Floating point/integer processor with divide and square root functions A processor (10) operable to calculate division and square root functions comprises a multiplier (48) having a multiplier array (116), a pipeline register (50), a correction generator (122), and a converter/rounder (52). The products generated by the mult... | 10/31/1989 |
| 4878192 | Arithmetic processor and divider using redundant signed digit arithmetic An arithmetic processor and an addition/subtraction circuit therefor are disclosed. The arithmetic processor comprises a plurality of the addition/subtraction units arranged in parallel, each unit being capable of carrying out addition (or subtraction) wi... | 10/31/1989 |
| 4873660 | Arithmetic processor using redundant signed digit arithmetic A high speed arithmetic processor which may compactly be fabricated on an LSI chip is disclosed. The arithmetic processor in a first-step arithmetic operation determines an intermediate carry (or intermediate borrow) for a higher order arithmetic operatio... | 10/10/1989 |
| 4866655 | Arithmetic processor and divider using redundant signed digit An arithmetic processor is disclosed for performing arithmetic operations utilizing an arithmetic operand represented by a signed digit expression having a plurality of digits which may have a positive, zero or negative value. The processor comprises: fir... | 09/12/1989 |
| 4860241 | Method and apparatus for cellular division A method and application for a cellular divider. The dividend is separated into P separate groups of b bits each. Division at the cellular level is accomplished on the groups in the respective order of place significance. Accordingly, the group representi... | 08/22/1989 |
| 4823301 | Method and circuit for computing reciprocals A circuit produces an output binary floating point number approximating with high accuracy the inverse of an input binary floating point number D in accordance with the expression (1/D).apprxeq.[(1/A)-C]+[C-(B/A2)], where the number A is a low ... | 04/18/1989 |
| 4817048 | Divider with quotient digit prediction A divider, which performs division in a base other than 2, that reduces in most cases the number of cycles it takes to generate each quotient digit. This involves predicting the minimum possible quotient digit in response to leading digits of the partial ... | 03/28/1989 |
| 4800515 | Circuit for operating finite fields A circuit for operating finite fields performs multiplication or division using an accumulator for storing an arbitrary element and an adder for performing modulo 2 addition, using the contents of the accumulator and a vector representation of the primiti... | 01/24/1989 |
| 4785412 | Double precision approximate quotient network A double precision approximate quotient network determines the quotient of a 2n bit number and an n bit number where the n bit number has a value of 2n-1 -2, 2n-1 -1, 2-1, or 2n+1. Apparatus determines the 2's c... | 11/15/1988 |
| 4761758 | Digital signal processor with divide function A digital signal processor which efficiently executes the division of a positive number in N+1 processor cycles where N is equal to the number of digits in the dividend. This is achieved by utlizing an arithmetic logic unit in the processor which is divid... | 08/02/1988 |
| 4761757 | Carry-save-adder three binary dividing apparatus A high-speed dividing apparatus includes first and second carry-save adders and a half carry-save adder and the outputs of the first carry-save adder are connected to the inputs of the second carry-save adder and half carry-save adder. The first carry-sav... | 08/02/1988 |
| 4760550 | Saving cycles in floating point division In dividing a pair of binary coded, hexidecimal floating point numbers, leading zero quotient bits are eliminated by comparing the magnitudes of the most significant digits of the fractional parts of the dividend and divisor after the dividend and divisor... | 07/26/1988 |
| 4754422 | Dividing apparatus A high-speed dividing apparatus includes a first, second and third carry save adders (CSA's) and the outputs of the first CSA are connected to the inputs of the second and third CSA's. The first CSA is capable of carrying out either the addition or the su... | 06/28/1988 |
| 4724529 | Method and apparatus for numerical division A method and apparatus for radix-ଲ non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involv... | 02/09/1988 |
| 4723243 | CRC calculation machine with variable bit boundary There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of... | 02/02/1988 |
| 4720831 | CRC calculation machine with concurrent preset and CRC calculation function There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of... | 01/19/1988 |
| 4718032 | Method and apparatus for effecting range transformation in a digital circuitry A range transformation method for transforming the normalized divisor in a division calculation to a range wherein the transformed value differs from one by no more than the quantity 2-n. The method and apparatus generate the transform multipli... | 01/05/1988 |
| 4682302 | Logarithmic arithmetic logic unit In a digital signal processing system, a logarithmic arithmetic logic unit is provided which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor ... | 07/21/1987 |
| 4589086 | Data processing system A data processing system having an arithmetic unit is designed for a multiplication of n-place numbers in 2's complement according to the Booth algorithm, and for division of unsigned numerals. A 2n-stage shift register is connected over a logical control... | 05/13/1986 |
| 4567568 | Apparatus for dividing the elements of a Galois field Data representing one element i of a Galois field GF(2m) are stored in a first linear shift register, and data representing another element j of the Galois field GF(2m) are stored in a second linea... | 01/28/1986 |
| 4503512 | Cellular division circuit An improved cellular division circuit is disclosed for performing divisional computation faster than prior art systems. The cellular division circuit includes a first adder for adding a dividend and a divisor thereby forming a first remainder and a second... | 03/05/1985 |
| 4484259 | Fraction bus for use in a numeric data processor A floating point, integrated, arithmetic circuit is organized around a file format having a floating point numeric domain exceeding that of any single or double precision floating point numbers, long or short integer words of BCD data upon which it must o... | 11/20/1984 |
| 4460970 | Digital data processing system using unique techniques for handling the leading digits and the signs of operands in arithmetic operations In a data processing system, an arithmetic logic means which determines the numbers of leading digits containing zero numeric values and the signs of operands supplied thereto and which discards the leading zero digits in such operands and performs the de... | 07/17/1984 |
| 4419918 | Synchronizing signal generator and an electronic musical instrument using the same A synchronizing signal generator includes a tape recorder which is adapted to record click signals in response to actuations of a manual switch. Counting clock signals go on while the click recorded signals are reproduced, especially during a length of ti... | 12/13/1983 |
| 4413326 | Floating point division control An improved means and method for accomplishing floating point calculations in computational apparatus includes a primary microprocessor and a secondary microprocessor, each with its own control ROM. The normal or fixed point calculations are handled by th... | 11/01/1983 |
| 4374427 | Divisor transform type high-speed electronic division system An electronic network division system is operated responsive to signals representing divisors and dividends. An input divisor signal is divided into a given number (N) of integers, the number (N) being selected on a basis of a desired accuracy index. Each... | 02/15/1983 |
| 4334285 | Divider for calculating by summation the quotient and remainder of an integer divided by a Mersenne number and a parallel processor system comprising memory modules, a Mersenne prime in number For division by a Mersenne number (2n -1), a divided P is expressed as: ##EQU1## A first summing unit sums up the coefficients ai 's to provide a sum of a carry multiplied by 2n and a sum portion less than 2n. | 06/08/1982 |
| 4306295 | Arrangement for measuring the ratio between a number of events occurring after each other in a first and a second series of events Arrangement for measuring the ratio between a number of sequential events occurring in a first series of events and a number of events in a second series of events, each series activating a pulse generator (P1, P2) included in the arrangement. The arrange... | 12/15/1981 |
| 4205303 | Performing arithmetic using indirect digital-to-analog conversion Circuitry and method for adding, subtracting, multiplying and/or dividing a plurality of multi-bit, arbitrarily signed, changeable, coded digital input signals representing numerical values to convert said signals into a single analog output signal of pre... | 05/27/1980 |
| 4137568 | Circuit for establishing the average value of a number of input values For averaging a selected number of input values, a circuit includes a counter which is enabled to count up to the selected number. During the counting, samples of input values are synchronously loaded into an accumulator circuit having shift capabilities.... | 01/30/1979 |
| 4118785 | Method and apparatus for digital attenuation by pattern shifting A digital attenuator is disclosed which is capable of having the output PCM signal attenuated nearly in proportion to the input PCM signal level based upon simple logic operations of where Pout = output PCM signal Pin = input PCM signal p... | 10/03/1978 |
| 4058714 | Selectively operated, clock-controlled repetitive calculator A portable calculator which performs selected arithmetic computations including addition, subtraction, multiplication and division includes a selectively operative clock circuit. When activated, the clock circuit repetitively performs the preselected math... | 11/15/1977 |
| 4011439 | Modular apparatus for accelerated generation of a quotient of two binary numbers A plurality of modular arrays, each structured from a common module, are connected together so as to form a binary quotient by successive approximations. For divisors that fall into that group of numbers that have reciprocals with a reasonably short perio... | 03/08/1977 |
| 4004140 | Digital attenuator A digital attenuator is disclosed which is capable of having the output PCM signal attenuated nearly in proportion to the input PCM signal level based upon simple logic operations of where Pout = output PCM signal Pin = input PCM signal p... | 01/18/1977 |
