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| Number | Title | Issue Date |
| 6173305 | Division by iteration employing subtraction and conditional source selection of a prior difference or a left shifted remainder A data processing apparatus iteratively forms quotient, includes data registers (200) for storing various initial and intermediate quantities, a multiplexer (215) for selecting data from one of two data registers, a barrel rotator (235) and an arithmetic ... | 01/09/2001 |
| 6161120 | Apparatus for performing a division operation, especially for three-dimensional graphics The present invention relates to arithmetical computing devices, and especially to a division operation in three-dimensional (3D) graphics. A division f(a,b)=a/b is calculated by an integrated division circuit. In order to decrease the chip area and calcu... | 12/12/2000 |
| 6138138 | High speed multiple determination apparatus In a multiple determination apparatus for determining whether or not a dividend is a multiple of a divisor which is represented by D=.multidot.2r where is an odd number and r is 0, 1, 2, . . . , a non-zero determination circuit d... | 10/24/2000 |
| 6125380 | Dividing method A method for dividing a dividend by a divisor and finding a dividing quotient and a dividing remainder is provided. The dividend has a low byte part and a high byte part and the divisor has a low byte part and a maximum digital value whose most significan... | 09/26/2000 |
| 6078941 | Computational structure having multiple stages wherein each stage includes a pair of adders and a multiplexing circuit capable of operating in parallel A modular computational structure includes a pipeline having first and second adder stages. Each adder stage includes a pair of adders which operate in parallel, and outputs ports of the first adder stage are coupled to input ports of the second adder sta... | 06/20/2000 |
| 6061781 | Concurrent execution of divide microinstructions in floating point unit and overflow detection microinstructions in integer unit for integer divide An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction in... | 05/09/2000 |
| 6060936 | Circuit and method for performing a divide operation with a multiplier A divider circuit provides a divide operation with a multiplier, counter and comparator. The divide operation of two values, x and y, to produce the value of x divided by y, x/y, is provided by sequentially multiplying y in the multiplier with values from... | 05/09/2000 |
| 6021487 | Method and apparatus for providing a signed integer divide by a power of two A method and apparatus to divide a signed integer by a constant power of two using conditionally-executed instructions to choose between a first result in the event that the dividend is a negative signed integer and a second result in the event that the d... | 02/01/2000 |
| 5969976 | Division circuit and the division method thereof A division method and circuit performs a division for signed data by adding or subtracting a divisor to or from the dividend or the partial remainder from the division, according to the sign of the divisor or the dividend and the partial remainder to acqu... | 10/19/1999 |
| 5928318 | Clamping divider, processor having clamping divider, and method for clamping in division A clamping divider has a bit shifter, a multiple accumulator (MAC), and an output circuit. When executing a division with the use of a clamp value of 2m, the bit shifter shifts one of the divisor and dividend of the division, and the MAC subtra... | 07/27/1999 |
| 5910910 | Circuit and method for rapid calculation of quotients and square roots A circuit and method for accelerating the division algorithm and square root operations relating to integers or floating-point numbers. Minimization of the number of gate delays per quotient digit generated is achieved through the use of triply-redundant ... | 06/08/1999 |
| 5903485 | Division by a constant A ripple through divider of a dividend by a constant is obtained by cascading a plurality of partial quotient tables. Each table incorporates the same divisor, so the divisor need not appear as an input. In one binary integer implementation for an n bit d... | 05/11/1999 |
| 5870323 | Three overlapped stages of radix-2 square root/division with speculative execution In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8 implementation cascades three partial remainder computation circuits and overlaps three quoti... | 02/09/1999 |
| 5831885 | Computer implemented method for performing division emulation A computer implemented method for generating a quotient. The method is exclusive of division operations. The method includes a first step of generating, in response to a first instruction, a first delta by performing an operation between a denominator and... | 11/03/1998 |
| 5825680 | Method and apparatus for performing fast division A method and apparatus for performing division in accordance with certain bandwidth requirements particular to an implementation is described. A pseudo pipelined approach for performing division using the SRT non-restoring division algorithm is described ... | 10/20/1998 |
| 5805488 | Method and structure for degrouping MPEG audio codes An MPEG audio/video decoder has memories, a signal processing unit (SPU) including a multiplier and a butterfly unit, a main CPU, and a memory controller which are time division multiplexed between decoding video and audio data. The decoder includes a deg... | 09/08/1998 |
| 5798955 | High-speed division and square root calculation unit A calculation unit speedily calculates a division or square root according to an iteration algorithm with a partial remainder expressed with the sum of a sum digit and carry digit. The calculation unit has a quotient selection logic circuit. The quotient ... | 08/25/1998 |
| 5787030 | Correct and efficient sticky bit calculation for exact floating point divide/square root results Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exac... | 07/28/1998 |
| 5771182 | Bit-serial digital compressor A bit-serial compressor (106) has a pre-divider circuit (208) receiving input serial data and generating a partial numerator. Divider circuit (210) divides the partial numerator by a denominator and generates a partial remainder that is fed back to the pr... | 06/23/1998 |
| 5757362 | Recursive digital filter using fixed point arithmetic There is provided a digital processor that includes a recursive filter having means for using fixed point arithmetic for performing division. The recursive filter includes means for saving a remainder after each division and multiplication operation and f... | 05/26/1998 |
| 5737255 | Method and system of rounding for quadratically converging division or square root A method and system which provides exactly rounded division and square root results for a designated rounding mode independently of a remainder, or equivalent calculation of the relationship between the remainder and zero, for predetermined combinations o... | 04/07/1998 |
| 5729481 | Method and system of rounding for quadratically converging division or square root A method and system which provides exactly rounded division and square root results for a designated rounding mode independently of a remainder, or equivalent calculation of the relationship between the remainder and zero, for predetermined combinations o... | 03/17/1998 |
| 5710730 | Divide to integer A system and method for providing an interruptible remainder instruction that can produce a quotient as well as a remainder. Remainders are computed through an iterative procedure. This procedure is carried out in a computer system's hardware by following... | 01/20/1998 |
| 5696712 | Three overlapped stages of radix-2 square root/division with speculative execution In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8 implementation cascades three partial remainder computation circuits and overlaps three quoti... | 12/09/1997 |
| 5689721 | Detecting overflow conditions for negative quotients in nonrestoring two's complement division A method of detecting anomalous overflow conditions is used, in an exemplary embodiment, in implementing in a 486-type microprocessor, nonrestoring two's complement division for negative quotients using 2n bit dividends and n bit divisors. Each interative... | 11/18/1997 |
| 5678055 | Method and device for generating Grobner bases to reduce memory usage and increase computing speed A method and device for generating the Grobner bases to reduce the memory usage and compute at a high speed. The method comprises the steps of a) selecting a prime number, b) computing the normalization format of the polynomial pair regarding p as the mod... | 10/14/1997 |
| 5675528 | Early detection of overflow and exceptional quotient/remainder pairs for nonrestoring twos complement division A system for the early detection of overflow or exceptional quotient/remainder pairs is used in conjunction with performing nonrestoring division using two's complement 2n bit dividends N and two's complement n bit divisors D--if early overflow is not sig... | 10/07/1997 |
| 5661674 | Divide to integer A system and method for providing an interruptible remainder instruction that can produce a quotient as well as a remainder. Remainders are computed through an iterative procedure. This procedure is carried out in a computer system's hardware by following... | 08/26/1997 |
| 5644639 | Device for carrying out a division This device is designed for carrying out a division of a dividend A formed by "m" words with a base "b" by a divisor D. It comprises an active memory (2), a multiplication member which forms part of a calculation unit (8) provided with a first input (x | 07/01/1997 |
| 5587940 | Non-heuristic decimal divide method and apparatus A method and apparatus for performing decimal division using a computer that does not have the capability to perform single instruction decimal multiplication or division. A divisor is normalized such that the value of the first digit of the divisor is no... | 12/24/1996 |
| 5555516 | Multipurpose error correction calculation circuit A bit-oriented error correction calculation circuit performs numerous mathematical operations including bit-oriented convolutions, inversions, multiplications, additions, and bi-directional basis conversions. The circuit includes three banks of registers ... | 09/10/1996 |
| 5524091 | Accurate digital divider A digital divider for forming the quotient (Q) of two numbers (A,B) includes means providing values (Q+1, Q-1) of the quotient with possible rounding errors added to or subtracted therefrom. Selector switching means is arranged to select one of the values... | 06/04/1996 |
| 5513132 | Zero latency overhead self-timed iterative logic structure and method A novel third phase of CMOS domino logic is identified and used in the logic system of the present invention to store data. The use of this third phase in addition to the normally used precharge and logic evaluation phases, provides a logic structure of c... | 04/30/1996 |
| 5499202 | Residue circuit A residue circuit takes weights of even number bits of a dividend as 1 and weights of odd number bits of the dividend as 2. The circuit includes a plurality of adders for summing bits having weight 1 to output weight 1 at a summing output and weight 2 at ... | 03/12/1996 |
| 5495488 | Arithmetic circuit having a simple structure for producing an error numeric value polynomial and an error locator polynomial In an arithmetic circuit for producing an error numeric value polynomial and an error locator polynomial in accordance with Euclid's algorithm, a first producing section (11) produces a quotient polynomial and a remainder polynomial which are obtained on ... | 02/27/1996 |
| 5485414 | Divider circuit which calculates an integral quotient of an integral divisor A divider circuit which calculates an integral quotient of an integral divisor and an integral dividend. A first multiplication unit calculates products of the integral divisor and all n-bit pattern values of an n-bit pattern, where n is a predetermined n... | 01/16/1996 |
| 5481745 | High speed divider for performing hexadecimal division having control circuit for generating different division cycle signals to control circuit in performing specific functions A divider comprising a first and second normalizing circuits (5, 6) each which holds a hexadecimal-normalized mantissa data of a dividend and divisor respectively, a selector (7) which inputs the mantissa outputted from the first normalizing circuit (5), ... | 01/02/1996 |
| 5467297 | Finite field inversion An inversion circuit (212) determines an inverse B-1 of an m-bit symbol B, the symbol B being expressed in a dual basis representation. Inversion circuit (212) includes an iterative convolution circuit (124A, 124B, 124C) to which the symbol B i... | 11/14/1995 |
| 5467299 | Divider and microcomputer including the same A subtraction-shift-type divider using a dividend or partial remainder represented by signed digits taking any of the values -1, 0, 1 and a divisor by twos complement representation. A selector, responding to values of a quotient digit at respective time ... | 11/14/1995 |
| 5444647 | Multiplier circuit and division circuit with a round-off function A multiplier circuit has a smaller circuit size and operates at a higher speed. An addition processing part (31b) to which a partial product group 6 is inputted includes at its first stage half adders (7a) and (7c) and a rounding half adder (13). The addi... | 08/22/1995 |
