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| Number | Title | Issue Date |
| 7065546 | Method of performing quantization within a multimedia bitstream utilizing division-free instructions Methods for enhancing the performance of quantization operations by converting division operations to a combination of multiplication and shift operations, which are preferably performed on a processor supporting single-instruction multiple-data (SIMD) instructions.... | 06/20/2006 |
| 7058677 | Method and apparatus for selectible quantization in an encoder A method for selectable quantization for use in an encoder for compressing video and/or audio data includes processing that begins by receiving discrete cosine transform data of an encoded signal. The processing continues by obtaining a quantization table. The proce... | 06/06/2006 |
| 7039666 | Circuitry for carrying out at least one of a square root and a division operation The invention provides circuitry for carrying out at least one of a square root operation and a division operation. The circuitry utilizes a carry slave adder and a carry propagate adder part. The carry save adder and the carry propagate adder part are arranged in p... | 05/02/2006 |
| 7020281 | Timing attack resistant cryptographic system A method for determining a result of a group operation performed an integral number of times on a selected element of the group, the method comprises the steps of representing the integral number as a binary vector; initializing an intermediate element to the group ... | 03/28/2006 |
| 7016930 | Apparatus and method for performing operations implemented by iterative execution of a recurrence equation The present invention provides an apparatus and method for performing an operation on an operand or operands in order to generate a result, in which the operation is implemented by iterative execution of a recurrence equation. In each iteration, execution of the rec... | 03/21/2006 |
| 7013320 | Apparatus and method for remainder calculation using short approximate floating-point quotient An apparatus and method for creating lookup tables of approximate floating-point quotients which exactly represent the underlying value, within the range of the specified precision. The lookup tables are created without any extraneous data beyond what is needed and ... | 03/14/2006 |
| 7007058 | Methods and apparatus for binary division using look-up table Improved methods of operating a digital data processor to perform binary division include estimating reciprocals of at least selected divisors based on value accessed from a look-up table. For divisors in a first numerical range, the estimation can be based on a val... | 02/28/2006 |
| 6973648 | Method and device to process multidimensional array objects A method for processing a multidimensional array object in which a multidimensional array is implemented by an array of array objects. The multidimensional array object comprises array objects which constitute the multidimensional array. Flags representing that it i... | 12/06/2005 |
| 6970179 | Method and apparatus for the scaling up of data A method, system, and data structure for the scaling up of data is provided. A block of transformed data samples is received wherein the transformed data samples represent original data samples. One of at least two tables of constants is selected wherein each table ... | 11/29/2005 |
| 6970525 | High-speed, high granularity baud clock generation A baud clock (15) for use by a serial communication interface (67) is generated by dividing a base clock of the serial communication interface by one of a plurality of possible composite divisors (DEG). Each composite divisor is indicative o... | 11/29/2005 |
| 6968492 | Hardware-efficient CRC generator for high speed communication networks A cyclic redundancy check (CRC) generator, in accordance with a specific embodiment of the present invention, generates a 32-bit CRC for each packet whose data bytes are carried over a 128-bit bus by first dividing the data bytes by a 123nd degree generat... | 11/22/2005 |
| 6963999 | Source coding to provide for robust error recovery during transmission losses A method and system are described for a multiple level shuffling process of a signal that provides for robust error recovery. A signal is defined as multiple levels wherein each level comprises a frame, a plurality of pixels, and a plurality of bits. In one embodime... | 11/08/2005 |
| 6954772 | Method and apparatus for performing modular division One embodiment of the present invention provides a system that performs modular division. This system contains a number of registers, including: a register A that is initialized with a value X; a register U that is initialized with a value Y; a register B that is in... | 10/11/2005 |
| 6922773 | System and method for encoding constant operands in a wide issue processor For use in a data processor comprising an instruction execution pipeline comprising N processing stages, a system and method of encoding constant operands is disclosed. The system comprises a constant generator unit that is capable of generating both short constant ... | 07/26/2005 |
| 6918018 | 64-bit single cycle fetch scheme for megastar architecture The 64-bit single cycle fetch method described here relates to a specific ‘megastar’ core processor employed in a range of new digital signal processor devices. The ‘megastar’ core incorporates 32-bit memory blocks arranged into separate entities or banks. B... | 07/12/2005 |
| 6918024 | Address generating circuit and selection judging circuit An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the... | 07/12/2005 |
| 6907442 | Development system of microprocessor for application program including integer division or integer remainder operations A microprocessor (10) comprises a compiler (4), which, for a source program including an integer division q=int(a÷b)(int( ) is a function discarding figures below decimal point in parentheses) for dividing integer a, expressed in N bits, by integer co... | 06/14/2005 |
| 6771094 | Devices and methods with programmable logic and digital signal processing regions A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly i... | 08/03/2004 |
| 6751645 | Methods and apparatus for performing pipelined SRT division An SRT division unit for performing a novel SRT division algorithm is presented. The novel SRT division algorithm comprises a method for performing SRT division using a radix r. As one skilled in the art will appreciate, the radix r dictates the number of quotient-b... | 06/15/2004 |
| 6711603 | Fractional, arithmetic unit, fractional arithmetic method, set-up engine for handling graphic images and computer-readable medium A fractional arithmetic unit for performing fractional arithmetic operations of different numerators and a common denominator with different precisions as required, the fractional arithmetic unit, including a reciprocal number arithmetic logic unit; and a multiply a... | 03/23/2004 |
| 6691144 | Dual use dual complex multiplier and complex divider A circuit performs complex division and dual complex multiplication. The circuit has a plurality of multipliers. Each of the plurality of multipliers is used in both the complex division and the dual complex multiplications. The circuit also has a plurali... | 02/10/2004 |
| 6687728 | Method and apparatus for arithmetic operation and recording medium of method of operation An integer Z101 is divided by an integer I102 to obtain a remainder R109. The integer I102 includes a polynomial of power of a basic operational unit of a computer. In this way, the integer I for divisor is limited based on the basic operational unit of t... | 02/03/2004 |
| 6687727 | Method and apparatus for arithmetic operation and recording medium of method of operation An integer Z101 is divided by an integer I102 to obtain a remainder R109. The integer I102 includes a polynomial of power of a basic operational unit of a computer. In this way, the integer I for divisor is limited based on the basic operational unit of t... | 02/03/2004 |
| 6658444 | Method and apparatus for performing a mask-driven interval division operation One embodiment of the present invention provides a system for performing a division operation between arithmetic intervals within a computer system. The system operates by receiving interval operands, including a first interval and a second interval, wher... | 12/02/2003 |
| 6625633 | Divider and method with high radix A high radix divider capable of reducing the size of the circuit of a quotient/remainder judgement unit in a radix 2k restoring division divider for finding a quotient k number of bits at a time, comparing multiples B, 2B, and 3B of a divisor B... | 09/23/2003 |
| 6604121 | Digital division device and method using a reduced-sized lookup table Devices and methods are provided for estimating a high-precision quotient using a smaller-than-conventional lookup table. The devices include a numerator register feeding a numerator value (as a succession of bits or words) into a forward signal path. The... | 08/05/2003 |
| 6564239 | Computer method and apparatus for division and square root operations using signed digit Computer method and apparatus for performing a square root or division operation generating a root or quotient is presented. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient di... | 05/13/2003 |
| 6549926 | SRT divider having several bits of each partial remainder one-hot encoded to minimize the logic levels needed to estimate quotient bits A Sweeney, Robertson, Tocher (SRT) divider for use in a computer system has recoding circuitry to recode the three most significant bits of the dividend into one-hot form as the dividend is loaded into a quotient/partial remainder register. With each cloc... | 04/15/2003 |
| 6538470 | Devices and methods with programmable logic and digital signal processing regions A programmable logic integrated circuit device ("PLD") includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are u... | 03/25/2003 |
| 6529929 | Quantization device and method using prime number dividers A quantization circuit includes a set of prime number dividers that can be implemented as look-up tables and a shifter. A shifter implements divisions by prime number (two) and by powers of two. Multiplexing circuitry interconnects the prime number divide... | 03/04/2003 |
| 6477556 | Method and apparatus for arithmetic operation and recording medium of method of operation An integer Z101 is divided by an integer I102 to obtain a remainder R109. The integer I102 includes a polynomial of power of a basic operational unit of a computer. In this way, the integer I for divisor is limited based on the basic operational unit of t... | 11/05/2002 |
| 6470372 | Method for the performance of an integer division A method for performing in a modular arithmetic coprocessor an integer division of a first binary data element by a second binary data element. The result is obtained by making an iterative loop of operations including an integer division of the first dat... | 10/22/2002 |
| 6457036 | System for accurately performing an integer multiply-divide operation A system for accurately and efficiently determining the result of an integer multiple-divide operation having the form of (A*B)/C is disclosed. If the values of A, B, and C provide for an easy solution (e.g., A, B, or C are zero, A equals C or B equals C,... | 09/24/2002 |
| 6446106 | Seed ROM for reciprocal computation A method and apparatus for performing a divide operation in a computer are described. The apparatus includes a first memory containing estimated reciprocal terms, and a second memory containing reciprocal error terms. An adder adds a selected estimated re... | 09/03/2002 |
| 6427220 | Method and apparatus for prml detection incorporating a cyclic code Apparatus and method for correcting errors in data recovered from a magnetic medium includes detecting the data recovered from the read wave form, and performing an arithmetic operation such as division on the recovered data sequence to determine any non-... | 07/30/2002 |
| 6360241 | Computer method and apparatus for division and square root operations using signed digit The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient dig... | 03/19/2002 |
| 6321245 | Method and system for performing fast division using non linear interpolation The present invention discloses a method and a system for performing fast division using non linear interpolation. A storage stores x-axis and y-axis coordinates (X0, Y0) of a plurality of non uniform interpolation points, and x-axis and y-axis coordinate... | 11/20/2001 |
| 6256656 | Apparatus and method for extending computational precision of a computer system having a modular arithmetic processing unit The integers involved in the computation are embedded into a modular system whose index (i.e., its modulus) is an integer M that is bigger than all of these integers involved. In other words, these integers are treated not as belonging to ordinary integer... | 07/03/2001 |
| 6240338 | Seed ROM for reciprocal computation A method and apparatus for performing a divide operation in a computer are described. The apparatus includes a first memory containing estimated reciprocal terms, and a second memory containing reciprocal error terms. An adder adds a selected estimated re... | 05/29/2001 |
| 6175850 | Scheme for carrying out modular calculations based on redundant binary calculation A scheme for carrying out modular calculations which is capable of carrying out modular calculations using redundant binary calculation even when a number of bits of the mantissa (dividend) is larger than a number of bits of the modulus (divisor). In this... | 01/16/2001 |
