Celebrity Inventors
Mark Twain (Samuel L. Clemens) received Patent No. 121,992 for "An Improvement in Adjustable and Detachable Straps for Garments." He later received two more patents: one for a self-pasting scrapbook and one for a game to help players remember important historical dates.
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| Number | Title | Issue Date |
| 8078662 | Multiplier product generation based on encoded data from addressable location For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number, wherein the encoded data is based at least in part on data that corresponds... | 12/13/2011 |
| 7840629 | Methods and apparatus for providing a booth multiplier Methods and apparatus for converting a radix 2 multiplier to respective groups of radix 4 encoded bits representing numbers of the group consisting of −2, −1, 0, 1, 2, wherein the set of encoded bits includes: a first bit that is true when the associated number ... | 11/23/2010 |
| 7809783 | Booth multiplier with enhanced reduction tree circuitry Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. A modified Booth multiplication system and process determine a multiplicand, A, and a multiplier, B. Radix-m, (e.g., radix-4)... | 10/05/2010 |
| 7797366 | Power-efficient sign extension for booth multiplication methods and systems Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., code division multiple access) system. Power-efficient sign extension for Booth multiplication processes involves applying a sign bit in a ... | 09/14/2010 |
| 7519648 | Encoder for a multiplier An encoder of a multiplier may include an operator generating unit for encoding a plurality of received multiplier data to output a plurality of operators. The encoder may include a partial-product data generating unit that generates a sign selecting operator from t... | 04/14/2009 |
| 7480691 | Arithmetic device for multiple precision arithmetic for Montgomery multiplication residue arithmetic In an arithmetic device which performs a multiplication of a multiplicand A and a multiplier B expressed by bit patterns using a secondary Booth algorithm, an encoder selects a partial product indicating −A when the value of i specifying three consecutive bits of ... | 01/20/2009 |
| 7433912 | Multiplier structure supporting different precision multiplication operations A unified data flow is provided that allows multiplication of SIMD and non-SIMD multiplies in one multiplier. The multiplies may be both integer and floating point operations. The multiplier is partitionable having a plurality of sub-trees. The multiplier is configu... | 10/07/2008 |
| 7337230 | Method and system for eliminating redundant rules from a rule set A computer implemented method and system determines whether a rule R is redundant with respect to a rule set S containing a plurality of non-redundant rules each defining tests for performing on a corresponding numeric field. A new rule set S′ is generated contain... | 02/26/2008 |
| 7334200 | Low-error fixed-width modified booth multiplier A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. ... | 02/19/2008 |
| 7330867 | Method and device for floating-point multiplication, and corresponding computer-program product In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to ... | 02/12/2008 |
| 7313585 | Multiplier circuit A multiplier circuit is disclosed for multiplying a multiplicand by a multiplier. The multiplier circuit includes a partial product generator and a partial product adder. The partial product generator includes a first input to receive a multiplicand; a second input ... | 12/25/2007 |
| 7308471 | Method and device for performing operations involving multiplication of selectively partitioned binary inputs using booth encoding A digital circuit including a Booth encoder having inputs for receiving a plurality of adjacent bits of a first binary input number, and an encoder control input for allowing selection between multiplication of first and second binary input numbers and multiplicatio... | 12/11/2007 |
| 7308470 | Smaller and lower power static mux circuitry in generating multiplier partial product signals A multiplier circuit to receive a multiplier and a multiplicand comprises at least one Booth encoder circuit to encode a plurality of multiplier bits into four encoded outputs. The encoded outputs select Booth-multiply functions. The circuit also includes a pluralit... | 12/11/2007 |
| 7296049 | Fast multiplication circuits Fast multiplication of two operands may be achieved by an interstitial product generator that generates an interstitial product from each of a plurality of mult-ibit segments of a multiplier. Generation of a final product is made faster because fewer interstitial pr... | 11/13/2007 |
| 7272624 | Fused booth encoder multiplexer A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results... | 09/18/2007 |
| 7266580 | Modular binary multiplier for signed and unsigned operands of variable widths A method and apparatuses for performing binary multiplication on signed and unsigned operands of various lengths is discussed herein. It is a concept that may be split into two parts, the first of which is the multiplication hardware itself, a compact, less than-ful... | 09/04/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7237089 | SIMD operation method and SIMD operation apparatus that implement SIMD operations without a large increase in the number of instructions An operation method has processing for applying a same type of operation in parallel to N M-bit operands to obtain N M-bit operation results executed on a computer. Here, N is an integer equal to or greater than 2 and M is an integer equal to or greater than 1. The ... | 06/26/2007 |
| 7237229 | Debugging aid parallel execution of a plurality of iterations with source lists display corresponding to each iteration This invention makes debugging more efficient when an object program is intended for processing a loop made up of n groups of iteration-forming instructions. Instructions in the secondary assembler program each has a combination of a line number “;lx” and an ite... | 06/26/2007 |
| 7237216 | Clock gating approach to accommodate infrequent additional processing latencies A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal... | 06/26/2007 |
| 7233886 | Adaptive modeling of changed states in predictive condition monitoring An improved empirical model-based surveillance or control system for monitoring or controlling a process or machine provides adaptation of the empirical model in response to new operational states that are deemed normal or non-exceptional for the process or machine.... | 06/19/2007 |
| 7231414 | Apparatus and method for performing addition of PKG recoded numbers An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a fi... | 06/12/2007 |
| 7225217 | Low-power Booth-encoded array multiplier An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does no... | 05/29/2007 |
| 7218253 | Hardware efficient implementation of finite impulse response filters with limited range input signals Disclosed herein is a method and system to reduce the area and power dissipation in digital filters or multipliers. Compared to radix-4 Booth coding the proposed method reduces the number of partial products by one, if the input signal has certain limits on its rang... | 05/15/2007 |
| 7203714 | Logic circuit A CMOS logic circuit is disclosed wherein the number of kinds of basic parts is suppressed to five to allow designing of a circuit which operates at a high speed and repetitiveness of wiring lines is increased to allow designing of a circuit which is simple in circu... | 04/10/2007 |
| 7194088 | Method and system for a full-adder post processor for modulo arithmetic A full-adder post processor performs modulo arithmetic. The full-adder post processor is a hardware implementation able to calculate A mod N, (A+B) mod N and (A−B) mod N. The processor includes a full adder able to add the operands A and B while modulo reduction i... | 03/20/2007 |
| 7194498 | Higher radix multiplier with simplified partial product generator A circuit and methodology for higher radix multiplication with improved partial product generation. The invention relates to the design of a high precision multiplier for an arithmetic unit of a digital processor. ... | 03/20/2007 |
| 7191204 | Computing system using newton-raphson method A dividing circuit and square root extracting circuit using the Newton-Raphson method. The number of places of an initial value of the Newton-Raphson method is decreased, and a part of a multiplier is omitted. Therefore the circuit scale is reduced. A circuit dedica... | 03/13/2007 |
| 7191203 | Method and system for high-speed multiplication A system, method, and computer product for high-speed multiplication of binary numbers. A multiplier X is first encoded, and the encoded multiplier is then used in a multiplication process that yields the product. The encoding is performed in a manner that allows th... | 03/13/2007 |
| 7177894 | Switching activity reduced coding for low-power digital signal processing circuitry A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a switching-reduction circuit that outputs a signal to a subsequent digital circuit... | 02/13/2007 |
| 7167890 | Multiplier-based processor-in-memory architectures for image and graphics processing A Procesor-In-Memory (PIM) includes a digital accelerator for image and graphics processing. The digital accelerator is based on an ALU having multipliers for processing combinations of bits smaller than those in the input data (e.g., 4×4 adders if the input data a... | 01/23/2007 |
| 7139787 | Multiply execution unit for performing integer and XOR multiplication A multiply execution unit that is operable to generate the integer product and the XOR product of a multiplicand and a multiplier. The multiply execution unit includes a summing circuit for summing a plurality of partial products. The partial products may be Booth e... | 11/21/2006 |
| 7136893 | Decimal multiplication using digit recoding A system and methodology for decimal multiplication in a microprocessor comprising: a recoder configured to recode decimal digits of a first operand to a corresponding set of {−5 to +5}. The recoder also configured to recode decimal digits of a second operand to a... | 11/14/2006 |
| 7119576 | Devices and methods with programmable logic and digital signal processing regions A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly i... | 10/10/2006 |
| 7120894 | Pass-transistor logic circuit and a method of designing thereof A method of designing a logic circuit including pass transistors is disclosed. A logic group having a complementary variable in a given logical expression to be realized into the logic circuit is mapped using a multiplexer composed of a combination of the pass trans... | 10/10/2006 |
| 7111033 | Carry save adders A carry save adder circuit for reducing the number of inputs to a lower number of outputs, the carry save adder circuit including four carry save adders, the four carry save adders being arranged in two layers with the first and second carry save adders being arrang... | 09/19/2006 |
| 7096246 | Arithmetic unit for multiplying a first quantity X by a second quantity Y An arithmetic unit for multiplying a first quantity x by a second quantity y, the arithmetic unit including a Booth coder having a plurality of inputs for receiving a plurality bits of the second quantity and a plurality of outputs for providing Booth coded outputs;... | 08/22/2006 |
| 7080115 | Low-error canonic-signed-digit fixed-width multiplier, and method for designing same An error compensation bias circuit and method for a canonic signed digit (CSD) fixed-width multiplier that receives a W-bit input and produces a W-bit product. Truncated bits of the multiplier are divided into two groups (a major group and a minor group) depending u... | 07/18/2006 |
| 7069290 | Power efficient booth recoded multiplier and method of multiplication In the multiplier, a partial product circuit generates a partial product based on a multiplicand operand and outputs of a Booth recoder circuit, which operates on a multiplier operand. The partial product circuit ANDs the multiplicand with a zero Booth recoded outpu... | 06/27/2006 |
| 7062526 | Microprocessor with rounding multiply instructions A functional unit in a digital system is provided with a rounding Multiplication instruction, wherein a most significant product of first pair of elements is combined with a least significant product of a second pair of elements, the combined product is rounded, and... | 06/13/2006 |
