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| Number | Title | Issue Date |
| 8095587 | Performing rounding in an arithmetic operation An arithmetic unit comprising: an encoding circuit arranged to receive first and second operands each having a bit length of m bits and to generate therefrom a number n of partial products of bit length of 2m bits or less; an addition circuit having 2m columns each ... | 01/10/2012 |
| 8019805 | Apparatus and method for multiple pass extended precision floating point multiplication A floating point multiplier circuit includes partial product generation logic configured to generate a plurality of partial products from multiplicand and multiplier values. The plurality of partial products corresponds to a first and second portion of the multiplie... | 09/13/2011 |
| 7774399 | Shift-add based parallel multiplication A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors,... | 08/10/2010 |
| 7546331 | Low power array multiplier An array multiplier comprises a partial product array including a plurality of array elements and a final carry propagate adder. Operands smaller than a corresponding dimension of the partial product array are shifted toward the most significant row or column of the... | 06/09/2009 |
| 7315879 | Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and parallel multipliers A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate core (120) also includes a plurality of Booth decoder cells (110... | 01/01/2008 |
| 7284029 | 4-to-2 carry save adder using limited switching dynamic logic A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry s... | 10/16/2007 |
| 7277479 | Reconfigurable fir filter A series of digit processing units (DPUs) are connected to form a finite impulse response (FIR) filter. Each DPU includes a register, a multiplexer, and a coefficient multiplier. The register stores and delays an input digital signal to be filtered. The multiplexer ... | 10/02/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7240086 | Method of image format conversion and remote control device using the same A method of image format conversion and remote control device using the same. Addition terms for a first layer are derived from an image conversion table. Every two addition terms are assigned to an addition group, obtaining a plurality of addition groups. The two a... | 07/03/2007 |
| 7225217 | Low-power Booth-encoded array multiplier An enhanced Booth-encoded adder-array multiplier where the low transition probability partial-products are generated and the adder array has been reorganized to reduce power dissipation when the Booth-encoded input has a large dynamic range. The architecture does no... | 05/29/2007 |
| 7218159 | Flip-flop circuit having majority-logic circuit A flip-flop circuit having a majority-logic circuit is disclosed. The circuit further includes multiple master latches for writing in corresponding input signals, and one slave latch having an input connected to an output of the majority-logic circuit and an output ... | 05/15/2007 |
| 7216141 | Computing carry-in bit to most significant bit carry save adder in current stage A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the ... | 05/08/2007 |
| 7167890 | Multiplier-based processor-in-memory architectures for image and graphics processing A Procesor-In-Memory (PIM) includes a digital accelerator for image and graphics processing. The digital accelerator is based on an ALU having multipliers for processing combinations of bits smaller than those in the input data (e.g., 4×4 adders if the input data a... | 01/23/2007 |
| 7119576 | Devices and methods with programmable logic and digital signal processing regions A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly i... | 10/10/2006 |
| 7082592 | Method for programming programmable logic device having specialized functional blocks A programming method efficiently programs programmable logic devices of the type having specialized functional blocks. Those blocks may include multipliers and other arithmetic function elements, or may be various types of memory blocks. In order to efficiently prog... | 07/25/2006 |
| 7072929 | Methods and apparatus for efficient complex long multiplication and covariance matrix implementation A digital signal processor for computing various types of complex multiplication is described. The digital signal processor operates in conjunction with registers, a multiplier, an adder, and a multiplexer The Registers store first and second complex operands. The m... | 07/04/2006 |
| 7058677 | Method and apparatus for selectible quantization in an encoder A method for selectable quantization for use in an encoder for compressing video and/or audio data includes processing that begins by receiving discrete cosine transform data of an encoded signal. The processing continues by obtaining a quantization table. The proce... | 06/06/2006 |
| 7024446 | Circuitry for arithmetically accumulating a succession of arithmetic values A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the u... | 04/04/2006 |
| 7020788 | Reduced power option A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one... | 03/28/2006 |
| 7007172 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 02/28/2006 |
| 7003543 | Sticky z bit The indication of a status affected by the performance of an ALU mathematical operation is provided. The indication includes the setting and clearing of a status bit in a status register based on the production of an arithmetic result of zero by an ALU performing th... | 02/21/2006 |
| 6993071 | Low-cost high-speed multiplier/accumulator unit for decision feedback equalizers A multiplier device for multiplying one of a discrete set of digital level values with a filter coefficient in a filter device implemented in a decision feedback equalizer including (i) a decoder device for receiving a discrete digital level value to be multiplied a... | 01/31/2006 |
| 6993546 | Quantized nonlinear scaler A method of providing a low cost quantized nonlinear scaler for a continuous curve includes the steps of providing a quantized coefficient table representing an approximation of the nonlinear continuous curve; applying the table in hardware to locate coefficients in... | 01/31/2006 |
| 6976158 | Repeat instruction with interrupt A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of times that the loop is to be repeated. Alternatively, the repeat instruct... | 12/13/2005 |
| 6975679 | Configuration fuses for setting PWM options Configuration bits are provided that configure PWM outputs of a processor incorporating a PWM module. The configuration bits cause the PWM module to put the PWM outputs into tri-state, active high or active low modes when the PWM module is inactive or when individua... | 12/13/2005 |
| 6973471 | Method and apparatus for implementing signed multiplication of operands having differing bit widths without sign extension of the multiplicand A multiplier (42) forms a product from two signed operands without performing a sign extension of the multiplicand (A). A modified Booth's recoding of the multiplier operand (B) is begun immediately without being delayed by a sign extension operation. While r... | 12/06/2005 |
| 6952711 | Maximally negative signed fractional number multiplication A method and processor for multiplying two maximally negative fractional numbers to produce a 32-bit result are provided. Operands are fetched from a source location for operation of a multiplication operation. Result outputs corresponding to a maximally negative re... | 10/04/2005 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
| 6925553 | Staggering execution of a single packed data instruction using the same circuit A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, ... | 08/02/2005 |
| 6904442 | Method of implementing logic functions using a look-up-table An apparatus comprising one or more look-up-tables (LUTs). The LUTs may be configured to provide logical functions. The one or more LUTs are generally implemented within a multiport memory. ... | 06/07/2005 |
| 6748590 | Method for generating instruction sequences for integer multiplication The invention pertains to an improved method for generating ALU instruction sequences for performing integer multiplication. The invention analytically helps to find an optimal sequence of shift, add and subtract instructions for performing integer multiplication by... | 06/08/2004 |
| 6728744 | Wide word multiplier using booth encoding A multiplier for computing a final product of a first operand and a second operand comprising a multiplier array for forming a product of the first operand and second operand in carry-save form; a carry-save adder for adding said carry-save partial products and an a... | 04/27/2004 |
| 6651079 | High speed pipeline multiplier with virtual shift Disclosed is a method and apparatus for accomplishing high speed multiplication of binary numbers using a single clock cycle to achieve the same computational power provided by the multiple clock cycle shift register configurations or the asynchronous mul... | 11/18/2003 |
| 6567834 | Implementation of multipliers in programmable arrays Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of the silicon area consumed thereby. There is thus provided ... | 05/20/2003 |
| 6542028 | System and method for efficient demodulation and filtering of a received signal An efficient demodulation and low pass filter structure comprises a shift-add-negate structure that effectively multiplies each received sample by a combined demodulation and filter coefficient, and an accumulator that accumulates the products. Low pass f... | 04/01/2003 |
| 6484194 | Low cost multiplier block with chain capability This application describes a method of multiplying numbers represented in multiple-word chains. The multiplication scheme allows for the multiplication of both signed and unsigned numbers of varying lengths. The multiplier block 30 executes a 17-bit by 17... | 11/19/2002 |
| 6434586 | Narrow Wallace multiplier A multiplier including a processor that generates at least one N by M array of partial products. The processor includes a first section that performs a first operation that generates an N by M array of partial products representing low order bits, and a s... | 08/13/2002 |
| 6286346 | Interruptable multiply and/or divide operations for use with an interrupt in a medical device processor A method and apparatus including conditional add and conditional add/subtract instructions are provided for use in the instruction set of a medical device instruction processor. More specifically, the conditional add and add/subtract instructions are prov... | 09/11/2001 |
| 6263357 | Parallel multiplier A parallel multiplier includes m multiplexers and a plurality of adders. The multiplexers receive an n-bit multiplicand and n-bit zero (0) through two input terminals, respectively, and one (1) bit of a m-bit multiplier through a select terminal to select... | 07/17/2001 |
| 6249799 | Selective carry boundary An adder tree includes several partial product generators, each generating a bit of equal weight. An adder receives the bits and provides a carry bit to a logic unit. The logic unit propagates the carry bit to the next more significant column in response ... | 06/19/2001 |
