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| Number | Title | Issue Date |
| 8028015 | Method and system for large number multiplication Methods, apparatus and systems for large number multiplication. A multiplication circuit is provided to compute the product of two operands (A and B), at least one of which is wider than a width associated with the multiplication circuit. Each of the operands includ... | 09/27/2011 |
| 7330869 | Hybrid arithmetic logic unit Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: ... | 02/12/2008 |
| 7275076 | Multiplication logic circuit A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length col... | 09/25/2007 |
| 7269616 | Transitive processing unit for performing complex operations The present invention provides a circuit for a programmable transitive processing unit for performing complex functions, such as multiplication, pipelining of one or more values, and/or shift operations, wherein the circuit can be configured to be a constituent of a... | 09/11/2007 |
| 7202408 | Methods and electronic systems for fingering assignments Embodiments of the disclosure relate to assignment of fingering for performance of a musical piece. In one example, a processor of an electronic system receives a file having data relating to at least one musical piece. The processor parses the file and assigns keys... | 04/10/2007 |
| 7155601 | Multi-element operand sub-portion shuffle instruction execution An apparatus and method for performing a shuffle operation on packed data is described. In one embodiment, a 128-bit packed data operand having at eight data elements is accessed. In one embodiment, one of the data elements in the upper half of the data operand is s... | 12/26/2006 |
| 7139788 | Multiplication logic circuit A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length col... | 11/21/2006 |
| 7136888 | Parallel counter and a logic circuit for performing multiplication A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of co... | 11/14/2006 |
| 7124162 | Adder tree structure digital signal processor system and method A Wallace tree structure such as that used in a digital signal processor (DSP) is arranged to sum vectors. The structure has a number of adder stages, each of which may have half adders with two input nodes, and full adders with three input nodes. The structure is d... | 10/17/2006 |
| 7043520 | High-speed/low power finite impulse response filter A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response f... | 05/09/2006 |
| 7042246 | Logic circuits for performing threshold functions Logic circuit generating four binary outputs as four threshold functions of four binary inputs, including: first, second, third, and fourth threshold functions which are respectively high if at least one, two, three and all of the binary inputs are high; first logic... | 05/09/2006 |
| 6978426 | Low-error fixed-width modified booth multiplier A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. ... | 12/20/2005 |
| 6959315 | Self-timed digital processing circuits A self-timed data processing circuit module is provided. Data is provided to the data processing circuit along with a Req handshaking input. The data processing circuit has an isochronous processing delay for all data inputs. An example of a data processing circuit ... | 10/25/2005 |
| 6938061 | Parallel counter and a multiplication logic circuit A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinatins of each bit of a binary... | 08/30/2005 |
| 6925563 | Multiplication of modular numbers A circuit for the implementation of modular multiplication of numbers comprises an alternative formation of the algorithm first proposed by R. C. Montgomery. The modified Montgomery algorithm is implemented in one of a plurality of circuits comprising full adders, h... | 08/02/2005 |
| 6922717 | Method and apparatus for performing modular multiplication A method and apparatus for performing modular multiplication is disclosed. An apparatus in accordance with one embodiment of the present invention includes a modular multiplier including a plurality of independent computation channels, where the plurality of indepen... | 07/26/2005 |
| 6915322 | Multiplier capable of multiplication of large multiplicands and parallel multiplications of small multiplicands A multiply unit uses four multipliers independently to perform for four parallel multiplications of single-width operands or uses the four multiplier cooperatively with an adder to perform a multiplication of double-width operands. In alternative embodiments, the ad... | 07/05/2005 |
| 6912560 | Adder with improved overflow flag generation An adder includes a number of computational stages each associated with one or more bit positions. Particular ones of the computational stages generate a sum output signal and a primary carry-output signal of the adder. A flag generation circuit is coupled to at lea... | 06/28/2005 |
| 6909767 | Logic circuit Circuit for selecting a second set of binary inputs according to the number of high input signals applied to a first input set. A first subcircuit has the first input set, logic generating control output signals, each control output signal represents whether the fir... | 06/21/2005 |
| 6883011 | Parallel counter and a multiplication logic circuit A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binar... | 04/19/2005 |
| 6567834 | Implementation of multipliers in programmable arrays Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of the silicon area consumed thereby. There is thus provided ... | 05/20/2003 |
| 6535646 | Discrete cosine transform method and apparatus A linear transform apparatus for implementing a linear transform on input data values to produce linear transformed output data, the apparatus comprising: input means for inputting input data values one after another to each of a series of multiplication ... | 03/18/2003 |
| 6530011 | Method and apparatus for vector register with scalar values A method and an apparatus for implementing mixed scalar and vector values in a digital processing system. In one embodiment, a digital processing system, which contains processing unit and memories, is capable of identifying a first data in a first scalar... | 03/04/2003 |
| 6490608 | Fast parallel multiplier implemented with improved tree reduction schemes Parallel multipliers and techniques for reducing Wallace-trees in parallel multipliers to achieve fewer reduction stages. The parallel multipliers of the present invention, in one embodiment, require one fewer stage of reduction than conventional multipli... | 12/03/2002 |
| 6470371 | Parallel multiplier An improved parallel multiplier capable of operating an addition operation by connecting a plurality of dividers sequentially, thus providing more simple circuit and reducing operating time thereof, which includes NXM AND-gates each for ANDing each multip... | 10/22/2002 |
| 6385634 | Method for performing multiply-add operations on packed data A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The ... | 05/07/2002 |
| 6202078 | Arithmetic circuit using a booth algorithm A booth decoder decodes A or -A according to a booth algorithm, depending upon whether A×B or -A×B should be multiplied. A partial multiplier/partial adder circuit 30 generates partial products of A×B or -A×B following to a result of the decoding, and... | 03/13/2001 |
| 6167421 | Methods and apparatus for performing fast multiplication operations in bit-serial processors Bit-serial processors quickly multiply multiple-bit operands using significantly fewer clock cycles as compared to conventional bit-serial implementations. Exemplary embodiments process groups of operand bits simultaneously to provide the significant spee... | 12/26/2000 |
| 6151617 | Multiplier circuit for multiplication operation between binary and twos complement numbers A multiplier circuit multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating ... | 11/21/2000 |
| 6122655 | Efficient use of inverting cells in multiplier converter A multiplier generates an array of partial products. The partial products are reduced in a converter having cells defining rows and columns. Cells adjacent to adders alternate between a cell that provides non-inverted outputs and a cell that provides inve... | 09/19/2000 |
| 6066178 | Automated design method and system for synthesizing digital multipliers A computer-based method and system is disclosed that automates the design and layout of digital multiplier circuits. The preferred method utilizes an automatic design generator having a user interface which receives design requirements for a digital multi... | 05/23/2000 |
| 6035316 | Apparatus for performing multiply-add operations on packed data A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second storage areas. The mult... | 03/07/2000 |
| 6026483 | Method and apparatus for simultaneously performing arithmetic on two or more pairs of operands A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and comprises a partial product generator, a selection logic unit, and an adder. The multip... | 02/15/2000 |
| 5983256 | Apparatus for performing multiply-add operations on packed data A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The ... | 11/09/1999 |
| 5978827 | Arithmetic processing In a processor for performing operations including an addition of a plurality of multiple bit data, values on common places of a plurality of multiple bit data are entered in parallel into number detectors set for respective places, the number of the high... | 11/02/1999 |
| 5963744 | Method and apparatus for custom operations of a processor Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time multimedia capabilities while maintaining advantages of a special... | 10/05/1999 |
| 5953241 | Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a... | 09/14/1999 |
| 5944775 | Sum-of-products arithmetic unit A sum-of-products arithmetic unit includes a coefficient register, a data register, a multiplier, an adder, and a data bus used for the transfer of data to and from an external unit. Provision is made to allow addresses in the data register in which sum-o... | 08/31/1999 |
| 5935201 | Multiplier circuit for multiplication operation between binary and twos complement numbers A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic g... | 08/10/1999 |
| 5928317 | Fast converter for left-to-right carry-free multiplier A multiplier generates an array of partial products. The partial products are reduced in the more significant side of the array assuming a carry-out from the less significant side of the array as taking on a first state to produce a first set of reduced p... | 07/27/1999 |
