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| Number | Title | Issue Date |
| 4495593 | Multiple bit encoding technique for combinational multipliers A four member encoding set is disclosed which allows the construction of combinational monolithic multipliers with a significant reduction in the number of devices required. The reduced device and wire count in the present technique allows a multiplier ci... | 01/22/1985 |
| 4475167 | Fast coefficient calculator for speech A digital circuit to approximate the product of two numbers by shifting the bits in one number to higher significance positions by an amount equal to the bit position of the most significant "one" in the other number, useful in digital speech recognition ... | 10/02/1984 |
| 4449194 | Multiple point, discrete cosine processor A discrete cosine processor for video signals and the like wherein each term of a discrete cosine transform matrix is approximated by a power of 2 terms so that all mathematical steps are performed by shifting and/or subtracting digital data. The apparatu... | 05/15/1984 |
| 4441158 | Arithmetic operation circuit There is disclosed an arithmetic operation circuit including an adder for performing a multiplication and a division. A one stage arithmetic cell group is formed by connecting eight arithmetic cells. Eight stage arithmetic cell groups are set in the obliq... | 04/03/1984 |
| 4366549 | Multiplier with index transforms modulo a prime or modulo a fermat prime and the fermat prime less one An asynchronous data-processing system for multiplying two binary numbers, by a use of read-only memories storing tables of data for transforming the numbers into exponents of a prime number. The exponents are added and then transformed back into the term... | 12/28/1982 |
| 4322810 | Digital filters with reduced multiplier circuitry A digital filter comprises a circuit means for applying a plurality of binary coded weights to a binary coded input data. The circuit means is constructed such that any of integer amounting to the number of bits of the binary coded weight data or to the n... | 03/30/1982 |
| 4313174 | ROM-Based parallel digital arithmetic device A fully-parallel digital arithmetic device for obtaining the square, C2, of a value, C, via parts of the value C and involving a reduction in memory requirements. Three square function ROM's are employed, one responsive to the most significant-... | 01/26/1982 |
| 4293922 | Device for multiplying binary numbers A fast, parallel operating device for multiplying binary coded numbers. The numbers are divided into groups of n bits of directly successive significance levels. Subsequently, all feasible combinations of one group of the first number and one group of the... | 10/06/1981 |
| 4291387 | Analog to digital conversion weighting apparatus A bucket brigade A/D weighting function multiplier which provides a simultaneous A/D conversion and multiplication by a weighting function in a continuous pipe line fashion, is disclosed. Each converted bit from the A/D converter is utilized by the multip... | 09/22/1981 |
| 4283770 | Signal processor for digital echo canceller A processor for an echo canceller generates an estimate of an actual echo on an echo path and applies the same to a subtractor circuit in the path to cancel the echo. To generate the echo estimate, the processor multiplies A-law digitally encoded samples ... | 08/11/1981 |
| 4276607 | Multiplier circuit which detects and skips over trailing zeros This invention is directed at an apparatus and method for detecting zero operand information and which also serves to detect trailing zeros. This circuit has application in computer circuitry, systems or the like wherein elongated information trains repre... | 06/30/1981 |
| 4269101 | Apparatus for generating the complement of a floating point binary number A complementer for floating point binary numbers utilizes two digital logic decision rules selected by the value of the power of the input number. The first decision rule is selected for an input power of -1 and constructs a power and mantissa determined ... | 05/26/1981 |
| 4229800 | Round off correction logic for modified Booth's algorithm A round off correction logic circuit is disclosed for inclusion within a floating point arithmetic binary digital multiplier implementing a modified Booth's algorithm for generating a final product of binary digits. The round off logic circuitry is connec... | 10/21/1980 |
| 4216531 | Finite field multiplier A multiplier for use with polynomials in an error correction system wherein the multiplier and multiplicand are first encoded from m bits to N bits, where N is greater than m, and wherein the multiplication is accomplished on a bit basis by arrays of AND ... | 08/05/1980 |
| 4215418 | Integrated digital multiplier circuit using current mode logic A parallel digital multiplier circuit fabricated in accordance with an advanced triple diffusion process providing feature geometry down to a minimum of two microns and junction depths of less than two microns, wherein a high packing density provided by t... | 07/29/1980 |
| 4202039 | Specialized microprocessor for computing the sum of products of two complex operands A specialized processor capable of computing a sum of products S=Σ&#b1;Pi where every product Pi is the product of two n-bit complex operands Ai+j Bi, the multiplier, and Ci+j Di, the multiplicand, where j=Ýa;-1. The processor includes an instruction... | 05/06/1980 |
| 4168530 | Multiplication circuit using column compression A high speed parallel operation, multiplication circuit is provided having a multiplier multiplexor which may function in combination with a column compressor for providing a resultant product, wherein, preferably, the multiplier multiplexor has been impl... | 09/18/1979 |
| 4163287 | Binary multiplier circuit including coding circuit A binary multiplier circuit wherein the product is expressed in coded form as soon as the linear (or non-coded) product is produced. When a twelve-bit binary number is multiplied by another twelve-bit binary number a twenty-four bit binary number is produ... | 07/31/1979 |
| 4156922 | Digital system for computation of the values of composite arithmetic expressions A digital system for computing of the values of composite arithmetic expressions, such as ##EQU1## XIJ WHERE N, K1, K2, ....., KN ARE ARBITRARY INTEGERS, ON NUMBERS XIJ IN A BINARY SYSTEM FOR APP... | 05/29/1979 |
| 4153938 | High speed combinatorial digital multiplier This disclosure relates to a high speed combinatorial 8 by 8 digital multiplier suitable for implementation on a single semiconductor chip including an encoder for implementing the Modified Booth Algorithm to encode the eight multiplier digits. The encode... | 05/08/1979 |
| 4118785 | Method and apparatus for digital attenuation by pattern shifting A digital attenuator is disclosed which is capable of having the output PCM signal attenuated nearly in proportion to the input PCM signal level based upon simple logic operations of where Pout = output PCM signal Pin = input PCM signal p... | 10/03/1978 |
| 4104729 | Digital multiplier The digital multiplier is of the add and shift type with a matrix type input in which a number of serial data words can be applied simultaneously to the multiplier enabling the multiplier to compute simultaneously the sum of a number of products. This mul... | 08/01/1978 |
| 4086474 | Multiplication technique in a data processing system Two numbers are multiplied together without first changing either of them, if negative, to a positive number, thereby minimizing the time required in the multiplication process. In the multiplication, depending upon the sign of the multiplier and the sign... | 04/25/1978 |
| 4086657 | Five-stage four-bit complex multiplier A multiplying system for complex numbers using four three-stage 4 × 4 bit 2's complement multipliers and a modified adder and subtractor. Two of the 2's complement multipliers are fed to the subtractor which produces a 9 bit output representing the real ... | 04/25/1978 |
| 4071904 | Current mode multiple-generating register A multiple-generating register generates one of several possible multiples of a binary number which is input thereto depending upon the informational content of a 3-bit control signal. For each data stage there exists a data selector circuit, a master/sla... | 01/31/1978 |
| 4041296 | High-speed digital multiply-by-device High speed digital multiply-by-three device comprising a sum generation unit associated with a carry look-ahead unit, the latter comprising means for generating the carry bit Ck.sub.+1 to be fed to the (k+1)th stage of said sum gener... | 08/09/1977 |
| 4034198 | Multiple generating register A multiple-generating register generates one of several possible multiples of a binary member which is input thereto in response to a respective one of a plurality of multiple-generating commands. The multiple-generating register comprises a control circu... | 07/05/1977 |
| 4031377 | Fast multiplier circuit employing shift circuitry responsive to two binary numbers the sum of which approximately equals the mantissa of the multiplier A multiplier for multiplying a fixed point multiplicand by a floating point multiplier utilizes decode logic which provides control signals related to two numbers, the sum of which is approximately equal to the mantissa of the multiplier. The multiplicand... | 06/21/1977 |
| 4013879 | Digital multiplier The digital CMOS/LSI synchronous serial multiplier includes a register to store an X-bit sign magnitude multiplier in parallel. The digital multiplier number can be entered into the register either serially or in parallel. A serial N-bit 2's complement mu... | 03/22/1977 |
| 4004140 | Digital attenuator A digital attenuator is disclosed which is capable of having the output PCM signal attenuated nearly in proportion to the input PCM signal level based upon simple logic operations of where Pout = output PCM signal Pin = input PCM signal p... | 01/18/1977 |
| 3997770 | Recursive digital filter Recursive digital filter comprising at least two digital delay devices, a multiplying device having two inputs which are coupled to one another in a common branch point, a summing device from which a sum signal is derived the magnitude of which is at leas... | 12/14/1976 |
| 3949209 | Multiple-generating register A multiple-generating register generates one of several possible multiples of a binary number which is input thereto in response to a respective one of a plurality of multiple-generating commands. The multiple-generating register comprises a control circu... | 04/06/1976 |
