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| Number | Title | Issue Date |
| 6925553 | Staggering execution of a single packed data instruction using the same circuit A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a macro instruction specifying an operation, and specifying a first and a second data operand in first and second registers, respectively, ... | 08/02/2005 |
| 6904442 | Method of implementing logic functions using a look-up-table An apparatus comprising one or more look-up-tables (LUTs). The LUTs may be configured to provide logical functions. The one or more LUTs are generally implemented within a multiport memory. ... | 06/07/2005 |
| 6826587 | Complex number multiplier The invention concerns a complex number multiplier receiving the binary number A, B, C and D complementarily coded in pairs so as to perform the complex multiplication (A+jB)*(C+jD). A first processing stage enables to perform the operations A−B, C−D, and A+B wh... | 11/30/2004 |
| 6823353 | Method and apparatus for multiplying and accumulating complex numbers in a digital filter The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a s... | 11/23/2004 |
| 6691144 | Dual use dual complex multiplier and complex divider A circuit performs complex division and dual complex multiplication. The circuit has a plurality of multipliers. Each of the plurality of multipliers is used in both the complex division and the dual complex multiplications. The circuit also has a plurali... | 02/10/2004 |
| 6675187 | Pipelined linear array of processor elements for performing matrix computations A pipelined linear array of processor elements (PEs) for performing matrix computations in an efficient manner. The linear array generally includes a head PE and a set of regular PEs, the head PE being a functional superset of the regular PE, with interco... | 01/06/2004 |
| 6567833 | Simultaneous computation of multiple complex number multiplication products An apparatus and method allow receivers to quickly acquire a pseudorandom noise signal. A receiver advantageously detects frequency shifts using a compact parallel process hardware implementation of a Discrete Fourier Transform (DFT). The simultaneous det... | 05/20/2003 |
| 6470370 | Method and apparatus for multiplying and accumulating complex numbers in a digital filter The invention provides a method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samp... | 10/22/2002 |
| 6449630 | Multiple function processing core for communication signals An apparatus for processing digital signals includes a multiplier having a first input and a second input and an output producing a product. An adder is connected to receive the product from the multiplier as a first input to produce a sum. A first regist... | 09/10/2002 |
| 6446106 | Seed ROM for reciprocal computation A method and apparatus for performing a divide operation in a computer are described. The apparatus includes a first memory containing estimated reciprocal terms, and a second memory containing reciprocal error terms. An adder adds a selected estimated re... | 09/03/2002 |
| 6434583 | Fast fourier transform apparatus and method A apparatus for providing a Fast Fourier Transform (FFT) and an inverse FFT is provided. The apparatus comprises a radix-N core. The radix-N core includes at least N multipliers. The radix-N core also includes a twiddle-factor lookup table that stores com... | 08/13/2002 |
| 6411979 | Complex number multiplier circuit A digital circuit for computing a function consisting of sums and differences of the products of a first vector of N multipliers and a second vector of M multiplicands, where at least one of N and M is greater than one include N multibit recoding circuits... | 06/25/2002 |
| 6349317 | Efficient radix-4 CORDIC vector rotators and computers of sine and cosine functions An improved radix-4 CORDIC rotator iteration stage, using answer digits {-3, -1, 1, 3} instead of the conventional choices of {-3, -2, -1, 0,1, 2, 3} or {-2, -1, 0, 1, 2}, thereby achieving constant magnitude amplification. The invention includes an answe... | 02/19/2002 |
| 6307907 | Complex multiplier Complex multiplication is performed using a multiplier by generating time division signals with a first clock and a second clock having a speed twice as fast as the first clock and operating the multiplier in a time division mode by the time division sign... | 10/23/2001 |
| 6272512 | Data manipulation instruction for enhancing value and efficiency of complex arithmetic A method and apparatus for performing complex arithmetic is disclosed. In one embodiment, a method comprises decoding a single instruction, and in response to decoding the single instruction, moving a first operand occupying lower order bits of a first st... | 08/07/2001 |
| 6237016 | Method and apparatus for multiplying and accumulating data samples and complex coefficients A method and apparatus for performing complex digital filters. According to one aspect of the invention, a method for performing a complex digital filter is described. The complex digital filter is performed using a set of data samples and a set of comple... | 05/22/2001 |
| 6122654 | Complex multiplication circuit A complex multiplication circuit of a calculation formula equivalent but different from the usual formula. The calculation formula is as follows: Pr={x(a+b)-b(x+y)} equivalent to (ax-by) Pi={y(a-b)+b(x+y)} equivalent to (ay+bx) Here, Input signal: x+jy Multiplier:a... | 09/19/2000 |
| 6055556 | Apparatus and method for matrix multiplication A system (400) alternatively performs real matrix operation in a first mode or performs complex matrix multiplication in a second mode. One input matrix (e.g., {B}) stays in a plurality of memory fields (430-k), while the other input matrix (e.g., {A}) is... | 04/25/2000 |
| 6041340 | Method for configuring an FPGA for large FFTs and other vector rotation computations A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables, permits the computation of vector rotation and large FFTs in a unitary ... | 03/21/2000 |
| 6021423 | Method for parallel-efficient configuring an FPGA for large FFTS and other vector rotation computations A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables permits the computation of vector rotation and large FFTs in an efficien... | 02/01/2000 |
| 5991788 | Method for configuring an FPGA for large FFTs and other vector rotation computations A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables, permits the computation of vector rotation and large FFTs in a unitary ... | 11/23/1999 |
| 5983253 | Computer system for performing complex digital filters A method and apparatus for performing complex digital filters. According to one aspect of the invention, a computer system generally having a transmitting unit, a processor, and a storage device is described. The storage device is coupled to the processor... | 11/09/1999 |
| 5936872 | Method and apparatus for storing complex numbers to allow for efficient complex multiplication operations and performing such complex multiplication operations The invention provides a method and apparatus for storing complex data in formats which allow efficient complex multiplication operations to be performed and for performing such complex multiplication operations. According to one aspect of the invention, ... | 08/10/1999 |
| 5802111 | Complex constellation point multiplier A complex constellation point multiplier (600) multiplies a complex number by a point in a digital modulation constellation. The desired constellation point is mapped to a digital control word. The complex number is connected to multiplicand input nodes (... | 09/01/1998 |
| 5777915 | Multiplier apparatus and method for real or complex numbers A multiplier for real or complex numbers is split at each data input into two equally large digit ranges to determine partial products in separate subfields. Within a rectangular partial-product field, the subfields are rearranged according to the real or... | 07/07/1998 |
| 5694349 | Low power parallel multiplier for complex numbers A high speed, low power parallel multiplier is described. The parallel multiplier includes specialized hardware circuitry designed to perform complex multiplication operations at high speeds. The parallel multiplier requires significantly less die area th... | 12/02/1997 |
| 5576983 | Arithmetic circuit for adaptive equalizer of LMS algorithm of reduced amount of operation An arithmetic circuit for adaptive equalizer of Least Mean Square (LMS) algorithm. Includes a real operation part computing a first product between a real part signal of a data sequence and a product of a real part signal of an error sequence and a step c... | 11/19/1996 |
| 5262976 | Plural-bit recoding multiplier A recoding method of two or more bit groups to reduce the number of partial products and their hardware implementation. Unique complementing scheme, pre-addition of complementing carriers and derivation of sign extensions also reduce hardware implementati... | 11/16/1993 |
| 5091875 | Fast fourier transform (FFT) addressing apparatus and method Apparatus for generating memory addresses for accessing and storing data in an FFT (Fast Fourier Transform) computation is provided. The FFT computation is typically performed by computing a plurality of FFT butterflies belonging to a plurality of ranks. ... | 02/25/1992 |
| 4970674 | Programmable windowing FFT device with reduced memory requirements An FFT building block useful in building FFT arrays includes a discrete-Fourier-transform device (DFT) having a plurality of DFT input lines, and a plurality of multipliers. Each multiplier has a multiplier-input line and a multiplier-output line. The mul... | 11/13/1990 |
| 4896287 | Cordic complex multiplier A CORDIC (COordinate Rotation DIgital Computer) subsystem for multiplication of two complex digital numbers B and C, where one number is the sum of real and imaginary data portions, expressed in rectangular form (say Cr or CI), and t... | 01/23/1990 |
| 4779218 | Complex arithmetic unit A complex arithmetic unit (CAU) for manipulating digital data representative of complex numbers. The CAU receives control signals and digital data representative of the real and imaginary parts of the complex operands from a host computer, and performs di... | 10/18/1988 |
| 4769779 | Systolic complex multiplier A complex multiplier includes a carry-sum systolic array (26) of multiplier cells for processing a multiplicand therethrough in accordance with a modified Booths algorithm. The multiplier performs two multiplications and two addition/substraction operatio... | 09/06/1988 |
| 4680727 | Complex multiplier for binary two's complement numbers A method and apparatus for multiplying two digital pairings representing complex numbers is described. The method includes preloading a memory with contents based on the second complex combination and the basis vector, and repeatedly addressing the memory... | 07/14/1987 |
| 4354249 | Processing unit for multiplying two mathematical quantities including at least one complex multiplier The processing unit includes at least one complex multiplier having hour multiplying circuits for multiplying the real and imaginary components of two complex vectors and combining the products to produce a complex output vector. Representing the input co... | 10/12/1982 |
| 4344151 | ROM-Based complex multiplier useful for FFT butterfly arithmetic unit A four-port digital complex multiplier useful for FFT butterfly arithmetic units and in which ROM's are employed as square function look-up tables. Each of the four ports is responsive to a respective one of the component values of two complex numbers. Th... | 08/10/1982 |
| 4215417 | Two-term vector multiplier A two-term vector multiplier for calculating Ax+BY and useful in FFT and digital filter circuits is disclosed. The variables A and B are converted into standard type-minimal representation codes which are then operated upon to generate selection signals a... | 07/29/1980 |
| 4181968 | Method and apparatus for forming convolutions of two complex number sequences using the fermat number transform A digital computing method and apparatus for complex numbers which, more particularly, comprises a technique and hardware for forming the complex linear vector product of two transformed sequences. The invention is designed for use in a computer system wh... | 01/01/1980 |
| 4027257 | Frequency domain automatic equalizer having logic circuitry An automatic equalizer for calculating the equalization transfer function of a transmission channel and applying same to equalize received signals. The initial calculation as well as the equalization proper are conducted entirely within the frequency doma... | 05/31/1977 |
