Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Number | Title | Issue Date |
| 8122078 | Processor with enhanced combined-arithmetic capability A method of operation within an integrated-circuit processing device having an enhanced combined-arithmetic capability. In response to an instruction indicating a combined arithmetic operation, the processor generates a dot-product of first and second operands, adds... | 02/21/2012 |
| 7917569 | Device for implementing a sum of products expression A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive... | 03/29/2011 |
| 7836117 | Specialized processing block for programmable logic device A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundament... | 11/16/2010 |
| 7797363 | Processor having parallel vector multiply and reduce operations with sequential semantics A processor comprises a plurality of arithmetic units, an accumulator unit, and a reduction unit coupled between the plurality of arithmetic units and the accumulator unit. The reduction unit receives products of vector elements from the arithmetic units and a first... | 09/14/2010 |
| 7747668 | Product-sum operation circuit and method A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi outp... | 06/29/2010 |
| 7739324 | Timing driven synthesis of sum-of-product functional blocks In one embodiment of the invention, an integrated circuit (IC) design tool is provided that has a sum-of-products (SOP) synthesizer. The SOP synthesizer receives expected arrival times of signals including partial product terms of each bit-vector of a SOP functional... | 06/15/2010 |
| 7711765 | Method and apparatus to perform multiply-and-accumulate operations A method and corresponding circuit for determining a final result for a desired series of multiply-and-accumulate (MAC) operations are based on counting the occurrence of products in the desired series of MAC operations, multiplying the counts by their corresponding... | 05/04/2010 |
| 7593978 | Processor reduction unit for accumulation of multiple operands with or without saturation A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the ... | 09/22/2009 |
| 7580968 | Processor with scaled sum-of-product instructions A method of performing a scaled sum-of-product operation in a processor in response to multiply-and-accumulate (MAC) instructions. The method includes accessing a first number, accessing a second number, and accessing a shift value. The first number is multiplied by... | 08/25/2009 |
| 7430578 | Method and apparatus for performing multiply-add operations on packed byte data A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. ... | 09/30/2008 |
| 7415542 | Micro-programmable filter engine having plurality of filter elements interconnected in chain configuration wherein engine supports multiple filters from filter elements A micro-programmable filter (MFE) engine includes multiple programmable filter elements and a microcode controller. The filter elements can be configured, controlled, and combined in different ways to implement different types of filters. The MFE preferably supports... | 08/19/2008 |
| 7395299 | System and method for efficient hardware implementation of a perfect precision blending function An apparatus and method for efficiently calculating an intermediate value between a first end value such that the area and time required to implement this operation is minimized is described. The apparatus and method may be used to efficiently multiply a value by a ... | 07/01/2008 |
| 7395298 | Method and apparatus for performing multiply-add operations on packed data A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor p... | 07/01/2008 |
| 7392275 | Method and apparatus for performing efficient transformations with horizontal addition and subtraction A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs... | 06/24/2008 |
| 7372922 | RSSE optimization using hardware acceleration A Reduced State Sequence Equalizer (RSSE) is implemented using a butterfly hardware accelerator (58) in the form of a butterfly to increase the efficiency of computing branch metrics (24) and the ACS (add, compare and select) function (26). Mult... | 05/13/2008 |
| 7366747 | Digital filter circuit and data processing method A digital filter circuit is capable of processing multi-channel data having different sampling frequencies. RAMs (random access memories) are provided which store data inputted thereto respectively, and the data outputted from the RAMs are alternately processed.... | 04/29/2008 |
| 7366746 | Finite impulse response filter method and apparatus Finite response filters (FIRs) are divided into partial filters that filter a same portion of image data to generate partial filtered results. The partial filtered results may be saved and later retrieved to generate complete filter outputs. ... | 04/29/2008 |
| 7318143 | Reuseable configuration data An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store opera... | 01/08/2008 |
| 7318080 | Split radix multiplication A first number is multiplied by a second number, by representing the first number as a first set of one or more W-bit wide numbers, and representing the second number as a second set of one or more W-bit wide numbers. Each of the W-bit wide numbers from the first se... | 01/08/2008 |
| 7315879 | Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and parallel multipliers A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate core (120) also includes a plurality of Booth decoder cells (110... | 01/01/2008 |
| 7296049 | Fast multiplication circuits Fast multiplication of two operands may be achieved by an interstitial product generator that generates an interstitial product from each of a plurality of mult-ibit segments of a multiplier. Generation of a final product is made faster because fewer interstitial pr... | 11/13/2007 |
| 7279212 | Playing surface structure and method of construction of a playing surface A playing surface structure (100) comprises, a surface carpet layer (102), a resin impregnated textile layer (104), a random pile layer (108) comprising a compact resin loaded fibre stratum (109) and a layer of stratified fibrous m... | 10/09/2007 |
| 7277540 | Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography An arithmetic apparatus for performing a long product-sum operation includes an integer unit arithmetic circuit, a finite field GF(2^m) based unit arithmetic circuit logically adjacent to the integer unit arithmetic circuit, a selector for selecting the integer unit... | 10/02/2007 |
| 7269615 | Reconfigurable input Galois field linear transformer system A reconfigurable input Galois field linear transformer system includes a Galois field linear transformer including a matrix of cells; a plurality of storage planes for storing control patterns representing a number of different functions; a storage plane selector ci... | 09/11/2007 |
| 7266580 | Modular binary multiplier for signed and unsigned operands of variable widths A method and apparatuses for performing binary multiplication on signed and unsigned operands of various lengths is discussed herein. It is a concept that may be split into two parts, the first of which is the multiplication hardware itself, a compact, less than-ful... | 09/04/2007 |
| 7262717 | Sample rate conversion combined with filter Digital filtering and sample rate conversion blocks are combined in order to reduce hardware and/or computational complexity. Input data samples provided at a first sample rate are converted to output data samples at a second sample rate unequal to the first sample ... | 08/28/2007 |
| 7242325 | Error correction compensating ones or zeros string suppression An error correction compensating ones or zeros string suppression system and method for use in a digital transmission system is herein disclosed. In digital transmission systems utilizing error control coding (ECC)/forward error correction (FEC) to reduce the number... | 07/10/2007 |
| 7234044 | Processor registers having state information Methods and apparatus are provided for implementing an efficient processor having state information included in each register. A processor has registers configured to hold both data and state information, such as carry and overflow information. State information and... | 06/19/2007 |
| 7216140 | Efficient implementation of n-point DCT, n-point IDCT, SA-DCT and SA-IDCT algorithms An efficient implementation of n-point discrete cosine transform, n-point inverse discrete cosine transform, shape adaptive discrete cosine transform and shape adaptive inverse discrete cosine transform algorithms for multimedia compression and decompression optimiz... | 05/08/2007 |
| 7216139 | Programmable logic device including multipliers and configurations thereof to reduce resource utilization In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and ca... | 05/08/2007 |
| 7212959 | Method and apparatus for accumulating floating point values A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for dir... | 05/01/2007 |
| 7168853 | Digital measuring system and method for integrated circuit chip operating parameters This invention relates to digitally measuring operating parameters, for example, temperature, within a semiconductor chip and making those measurements internally available to hardware, firmware, and software. ... | 01/30/2007 |
| 7167890 | Multiplier-based processor-in-memory architectures for image and graphics processing A Procesor-In-Memory (PIM) includes a digital accelerator for image and graphics processing. The digital accelerator is based on an ALU having multipliers for processing combinations of bits smaller than those in the input data (e.g., 4×4 adders if the input data a... | 01/23/2007 |
| 7164290 | Field programmable gate array logic unit and its cluster The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate un... | 01/16/2007 |
| 7124160 | Processing architecture having parallel arithmetic capability According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operand... | 10/17/2006 |
| 7120143 | Voice-over Internet protocol processor The present invention is directed to audio processing including IP telephony audio processing. Voice-over-IP terminals used in phone terminal applications benefit from a low-power implementation suitable for the limited chassis area of these devices. According to an... | 10/10/2006 |
| 7109987 | Method and apparatus for dual pass adaptive tessellation A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shad... | 09/19/2006 |
| 7111155 | Digital signal processor computation core with input operand selection from operand bus for dual operations A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features... | 09/19/2006 |
| 7111031 | Dual processor having a function calculating the sum of the results of a plurality of arithmetic operations A data driven information processor circulates a data packet therein, while in accordance with a previously prepared data flow program the processor performs a plurality of types of operation including performing an arithmetic operation on data and accumulating a re... | 09/19/2006 |
| 7111156 | Method and apparatus for multi-thread accumulation buffering in a computation engine A method and apparatus for enhancing flexibility of instruction ordering in a multi-thread processing system that performs multiply and accumulate operations is presented. A plurality of accumulation registers is provided for storing the results of an adder, wherein... | 09/19/2006 |
