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A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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| Number | Title | Issue Date |
| 7925687 | Reporting a saturated counter value A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a ma... | 04/12/2011 |
| 7860915 | Digital signal processing circuit having a pattern circuit for determining termination conditions A method for detecting a pattern from an arithmetic logic unit (ALU) in an integrated circuit. The method includes the steps of: generating an output from an ALU; bitwise comparing the ALU output to a pattern to produce a first output; inverting the pattern and comp... | 12/28/2010 |
| 7689640 | Method and apparatus for formatting numbers in microprocessors An apparatus for scaling numbers comprises register means for storing an operand to be scaled, bit shifting means for performing a right shift operation on the operand, rounding means, and decision means to test for the existence of at least one of an overflow and a... | 03/30/2010 |
| 7580967 | Processor with maximum and minimum instructions A method of operating a processor in a variable bit-length environment by performing a maximum limit function and minimum limit function. The method comprises accessing a most significant portion of a first number in a first register, wherein the most significant po... | 08/25/2009 |
| 7543014 | Saturated arithmetic in a processing unit In some embodiments a system comprises an overflow control bit, a programmable saturation control bit, a processing unit, and a saturation unit coupled to the processing unit. A selection unit may select the output of the processing unit or the output of the saturat... | 06/02/2009 |
| 7467178 | Dual mode arithmetic saturation processing A system and method for overflow and saturation processing during accumulator operations that reduces the error in a saturation operation. Upon overflow, additional guard bits used in conjunction with an accumulator allow a user to continue processing without any er... | 12/16/2008 |
| 7461118 | Arithmetic logic unit with merged circuitry for comparison, minimum/maximum selection and saturation for signed and unsigned numbers A saturation-capable arithmetic logic unit (ALU) includes a general-purpose comparator coupled to receive a data value and a saturation threshold value during a saturation operation. Using the general-purpose comparator of the ALU for saturation minimizes circuit ar... | 12/02/2008 |
| 7428567 | Arithmetic unit for addition or subtraction with preliminary saturation detection An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as respective less significant and more significant portions. The arithm... | 09/23/2008 |
| 7295689 | System and method for real-time processing and display of digital medical images A method of processing image data of a scanned object includes performing, in integer format, a pixel offset correction on the image data using unsigned saturation arithmetic to produce an image in integer format having negative value pixels clipped to a value of ze... | 11/13/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7233963 | Systems and methods for diffusing clipping error Systems and methods are provided for diffusing clipping error in a computing system. When a data set contains values which are to be restricted to a range, and the data set includes one or more values which are beyond the range, the invention provides methodology th... | 06/19/2007 |
| 7215801 | Method, system and apparatus for processing radiographic images of scanned objects A method, system and apparatus for processing a radiographic image of a scanned object is disclosed. A pixel offset correction is performed in integer format on the radiographic image using saturation arithmetic to produce an image in integer format with any negativ... | 05/08/2007 |
| 7206800 | Overflow detection and clamping with parallel operand processing for fixed-point multipliers A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixe... | 04/17/2007 |
| 7177893 | High-efficiency saturating operator A method for determining, by means of a circuit, a result sk+2 of an operation of the type s k + 2 = ... | 02/13/2007 |
| 7171438 | Method for recognition of full-word saturating addition and subtraction A method of formulating and solving equations that facilitate recognition of full word saturating addition and subtraction The method includes formulating, for each basis addition statement z=x+y or subtraction statement z=x−y, data flow equations that describe pr... | 01/30/2007 |
| 7149766 | Methods for detecting overflow and/or underflow in a fixed length binary field Methods of detecting overflow and/or underflow events are provided. The methods are preferably incorporated into a high-level programming language, but this is not necessary. In one embodiment, an increasing function that may cause overflow for a data element having... | 12/12/2006 |
| 7143335 | Add-compare-select arithmetic unit for Viterbi decoder An add-compare-select (ACS) arithmetic unit for a Viterbi decoder is provided. The ACS arithmetic unit includes two 2's complement adders for performing an operation on a state metric related to a bit value 0 and a state metric related to a bit value 1, respectively... | 11/28/2006 |
| 7124160 | Processing architecture having parallel arithmetic capability According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a number of arithmetic processors. A bitwise inverter is coupled to at least one of the first number of operand... | 10/17/2006 |
| 7120661 | Bit exactness support in dual-MAC architecture An arrangement (200) and method for bit exactness support in dual-MAC architecture by detecting when underflow or overflow conditions will occur, and for operating the dual-MAC arrangement in single-MAC mode for at least one cycle upon such detection. ... | 10/10/2006 |
| 7089277 | Computation circuit having dynamic range extension function A computation circuit which can obtain n+m-digit accumulation results by using an n-digit computation unit. This computation circuit comprises a computation unit which performs additions of n-digit data; an m-digit up/down counter; and a control circuit which uses t... | 08/08/2006 |
| RE39121 | Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation ins... | 06/06/2006 |
| 7051062 | Apparatus and method for adding multiple-bit binary-strings Apparatus for determining a value, a sign and an overflow status of an addition of at least three n-bit data inputs. The apparatus comprising: a first adder, for adding the at least three n-bit data inputs, to provide a first output having at least 2n bits; a second... | 05/23/2006 |
| 7047270 | Reporting a saturated counter value A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a ma... | 05/16/2006 |
| 7020788 | Reduced power option A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one... | 03/28/2006 |
| 7013321 | Methods and apparatus for performing parallel integer multiply accumulate operations According to the invention, a processing core that executes a parallel multiply accumulate operation is disclosed. Included in the processing core are a first, second and third input operand registers; a number of functional blocks; and, an output operand register. ... | 03/14/2006 |
| 7010786 | Predictive arithmetic overflow detection A method for arithmetic overflow detection includes receiving a first instruction defined for a first processor having a first base, where the instruction comprises an operator and at least one operand having an operand type. The method also includes indicating whet... | 03/07/2006 |
| 7007172 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 02/28/2006 |
| 7003543 | Sticky z bit The indication of a status affected by the performance of an ALU mathematical operation is provided. The indication includes the setting and clearing of a status bit in a status register based on the production of an arithmetic result of zero by an ALU performing th... | 02/21/2006 |
| 6996702 | Processing unit with cross-coupled ALUs/accumulators and input data feedback structure including constant generator and bypass to reduce memory contention A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. T... | 02/07/2006 |
| 6993545 | Digital filter with protection against overflow oscillation A digital filter having the capability to completely prevent the digital filter from generating the overflow oscillation by detecting positive and negative overflow propagating one or a plurality of bits by means of an overflow detecting circuit. When overflow is de... | 01/31/2006 |
| 6983300 | Arithmetic unit An arithmetic unit for adding a plurality of values to define a result, the arithmetic unit including circuitry for receiving the plurality of values; circuitry for adding the plurality of values to define a result, the result being within a first range; circuitry f... | 01/03/2006 |
| 6978287 | DSP processor architecture with write datapath word conditioning and analysis An improved digital signal processing (DSP) processor architecture is presented in which word conditioning (e.g., rounding, saturation, etc.) and analysis operations (e.g., block floating point analysis) are implemented in the write datapath to memory. By moving wor... | 12/20/2005 |
| 6975679 | Configuration fuses for setting PWM options Configuration bits are provided that configure PWM outputs of a processor incorporating a PWM module. The configuration bits cause the PWM module to put the PWM outputs into tri-state, active high or active low modes when the PWM module is inactive or when individua... | 12/13/2005 |
| 6976158 | Repeat instruction with interrupt A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of times that the loop is to be repeated. Alternatively, the repeat instruct... | 12/13/2005 |
| 6958718 | Table lookup operation within a data processing system A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result ... | 10/25/2005 |
| 6957238 | Method and system for deterministic pseudo-random valid entry resolution The present invention provides a method and system to select a valid entry in a deterministic pseudo-random approach. The method may randomly select one of numerous valid entries in order to ensure that no specific entry or set of entries is consistently ignored. Mo... | 10/18/2005 |
| 6952711 | Maximally negative signed fractional number multiplication A method and processor for multiplying two maximally negative fractional numbers to produce a 32-bit result are provided. Operands are fetched from a source location for operation of a multiplication operation. Result outputs corresponding to a maximally negative re... | 10/04/2005 |
| 6947962 | Overflow prediction algorithm and logic for high speed arithmetic units An algorithm and implementation is described of overflow prediction for addition without the use of an expensive addition operation. This overflow prediction is particularly applicable to the implementation of addition operation using the carry-save format in high s... | 09/20/2005 |
| 6941329 | Digital method for increasing the calculation accuracy in non-linear functions and hardware architecture for carrying out said method In a digital electronic method for increasing the calculation accuracy in non-linear functions and a system for performing the method, wherein an input format has a strictly defined word but the fixed point may be at different locations, the values are so processed ... | 09/06/2005 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
