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| Number | Title | Issue Date |
| 8005885 | Encoded rounding control to emulate directed rounding during arithmetic operations A processor, an instruction set architecture, an instruction, a computer readable medium and a method for implementing optimal per-instruction encoding of rounding control to emulate directed rounding are disclosed. In one embodiment, an apparatus designed to perfor... | 08/23/2011 |
| 7949701 | Method and system to perform shifting and rounding operations within a microprocessor A method and system to perform shifting and rounding operations within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to shift and round data within a source register unit of... | 05/24/2011 |
| 7912888 | Rounding computing method and computing device therefor A computing device has a rounding processor that inputs therein a set of plural (K) input data IN1 through INK comprising z bits. The rounding processor selects an ensured bit field depending upon the state of usage of each of specific areas A of upper z/2 bi... | 03/22/2011 |
| 7853636 | Digital signal processing circuit having a pattern detector circuit for convergent rounding An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked... | 12/14/2010 |
| 7822799 | Adder-rounder circuitry for specialized processing block in programmable logic device Adder/rounder circuitry for use in a programmable logic device computes a rounded sum quickly, and ideally within one clock cycle. The rounding position is selectable within a range of bit positions. In an input stage, for each bit position in that range, bits from ... | 10/26/2010 |
| 7487196 | Methods and apparatus for implementing a saturating multiplier Methods and apparatus are provided for implementing an efficient saturating multiplier associated with addition and subtraction logic. The result of the multiplier is saturated before accumulating. The result of the multiplier can be stored in a result register in u... | 02/03/2009 |
| 7467176 | Saturation and rounding in multiply-accumulate blocks Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value repres... | 12/16/2008 |
| 7467177 | Mathematical circuit with dynamic rounding Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding consta... | 12/16/2008 |
| 7342977 | Serial data transmitter with bit doubling A method is provided for transmitting serial data. The method includes receiving successive transmit data words, wherein each transmit data word has a plurality of bits. Each of the plurality of bits in each transmit data word is multiplied into a multiple number of... | 03/11/2008 |
| 7340498 | Apparatus and method for determining fixed point in mobile communication system Apparatus and method for determining a fixed point in a mobile communication system are disclosed. An initial fixed point is set through simulation and a saturation for an output of a target device is compared with a reference saturation. Then, the position of the i... | 03/04/2008 |
| 7313286 | Reversible DCT for lossless-lossy compression A reversible Discrete Cosine Transform (DCT) is described. The reversible DCT may be part of a compressor in a system. The system may include a decompressor with a reversible inverse DCT for lossless decompression or a legacy decompressor with an inverse DCT for los... | 12/25/2007 |
| 7272804 | Generation of RTL to carry out parallel arithmetic operations Computer-implemented method and system for generating an optimized description of an arithmetic function comprising at least two of an addition, a multiplication, and a rounding operation to be carried out on a plurality of data bits in a plurality of registers of a... | 09/18/2007 |
| 7272531 | Aggregation of asset use indices within a process plant A method of monitoring an entity within a process plant wherein the entity includes a plurality of lower level entities, includes acquiring a plurality of use indices, acquiring a plurality of weighting values, and creating an aggregate use index from a combination ... | 09/18/2007 |
| 7251369 | Recording medium having recorded thereon coded information using plus and/or minus rounding of images A recording medium having recorded thereon information of images coded by performing motion compensation is provided to obtain high quality images without error accumulation. Such information includes rounding method information specifying a positive rounding method... | 07/31/2007 |
| 7248742 | Encoding and decoding method and apparatus using plus and/or minus rounding of images An image decoding method is utilized to obtain high quality images without error accumulation. Such an image decoding method comprises receiving an encoded bitstream including information of P and B frames, and executing motion compensation by synthesizing a predict... | 07/24/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7236635 | Encoding and decoding method and apparatus using plus and/or minus rounding of images An image decoding method is utilized to obtain high quality images without error accumulation. Such an image decoding method comprises receiving an encoded bitstream including information of P and B frames, and executing motion compensation by synthesizing a predict... | 06/26/2007 |
| 7233704 | Encoding and decoding method and apparatus using plus and/or minus rounding of images An image decoding method is utilized to obtain high quality images without error accumulation. Such an image decoding method comprises receiving an encoded bitstream including information of P and B frames, and executing motion compensation by synthesizing a predict... | 06/19/2007 |
| 7221988 | Creation and display of indices within a process plant A process control system uses an asset utilization expert to collect data or information pertaining to the assets of a process plant from various sources or functional areas of the plant including, for example, the process control functional areas, the maintenance f... | 05/22/2007 |
| 7206646 | Method and apparatus for performing a function in a plant using process performance monitoring with process equipment monitoring and control A process control system uses a data collection and distribution system and an asset utilization suite to collect data or information pertaining to the assets of a process plant from various sources or functional areas of the plant including, for example, the proces... | 04/17/2007 |
| 7200274 | Encoding and decoding method and apparatus using plus and/or minus rounding of images An image decoding method is utilized to obtain high quality images without error accumulation. Such an image decoding method comprises receiving an encoded bitstream including information of P and B frames, and executing motion compensation by synthesizing a predict... | 04/03/2007 |
| 7184601 | Encoding and decoding method and apparatus using plus and/or minus rounding of images An image decoding method is utilized to obtain high quality images without error accumulation. Such an image decoding method comprises receiving an encoded bitstream including information of P and B frames, and executing motion compensation by synthesizing a predict... | 02/27/2007 |
| 7177889 | Methods and systems for efficient filtering of digital signals A method in a signal processor for filtering samples in a digital signal is provided. An approximate filtered sample is generated as a function of less than four samples of the digital signal. A correction is generated as a function of the less than four samples, an... | 02/13/2007 |
| 7174358 | System, method, and apparatus for division coupled with truncation of signed binary numbers A system, method, and apparatus for dividing and truncating a dividend by a divisor, wherein the magnitude of the divisor is a positive power of two, e.g., 2x, is presented herein. If the divisor is positive, the sign bit of the dividend is concatenated x... | 02/06/2007 |
| 7165086 | System, method, and apparatus for division coupled with rounding of signed binary numbers A system, method, and apparatus for efficient rounding of signed numbers is presented herein. If the divisor is positive, the dividend is added to one half of the magnitude of the divisor. If the divisor is negative, the complement of the dividend is added to one ha... | 01/16/2007 |
| 7161585 | Displacement data post-processing and reporting in an optical pointing device There is described a method of post-processing and reporting detected displacement in an optical pointing device as well as a sensing device for an optical pointing device implementing this method. Displacement is detected and a first count representative of a magni... | 01/09/2007 |
| 7155471 | Method and system for determining the correct rounding of a function A method and system is used to determine the correct rounding of a floating point function. The method involves performing the floating point function to a higher precision than required and examining the portion of extra precision in the result known as the discrim... | 12/26/2006 |
| 7155472 | Fixed-point quantizer for video coding A quantizer employs a scaled integral inverse ratio division for quantization of an input T by a quantization step Q. The quantizer forms an integral approximation q of 2r/Q by either trunc(2r/Q) or round(2r/Q). A multiplier multipli... | 12/26/2006 |
| 7130876 | Systems and methods for efficient quantization A method in a signal processor for quantizing a digital signal is provided. A fixed-point approximation of a value X÷Q is generated, wherein X is a fixed-point value based on one or more samples in the digital signal, and wherein Q is a fixed-point quantization par... | 10/31/2006 |
| 7117209 | Record trimming method, apparatus, and system to improve processing in a sort utility Control statements related to record input, output, filtering, and formatting in a data processing system are scanned by a parser to find one or more trimming control parameters referenced in the control statements. A record trimming module scans selected data recor... | 10/03/2006 |
| 7085794 | Low power vector summation method and apparatus An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement ... | 08/01/2006 |
| 7072518 | Encoding and decoding method and apparatus using plus and/or minus rounding of images An image decoding method is utilized to obtain high quality images without error accumulation. Such an image decoding method comprises receiving an encoded bitstream including information of P and B frames, and executing motion compensation by synthesizing a predict... | 07/04/2006 |
| RE39121 | Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation ins... | 06/06/2006 |
| 7047272 | Rounding mechanisms in processors An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial product reduction tree will generate carry results and provides a final output to a final adder ... | 05/16/2006 |
| 7035892 | Apparatus and method for reducing precision of data Methods and apparatus for reducing precision of an input signal, by comparing a portion of the input signal to a preselected threshold value, and determining a selectable bias responsive to the comparison. By combining a portion of the input signal with the selectab... | 04/25/2006 |
| 7020788 | Reduced power option A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one... | 03/28/2006 |
| 7013321 | Methods and apparatus for performing parallel integer multiply accumulate operations According to the invention, a processing core that executes a parallel multiply accumulate operation is disclosed. Included in the processing core are a first, second and third input operand registers; a number of functional blocks; and, an output operand register. ... | 03/14/2006 |
| 7007172 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 02/28/2006 |
| 6996597 | Increasing precision in multi-stage processing of digital signals Precision of multi-stage digital signal processing is increased by preserving least significant bits of one or more output samples of a particular processing stage, having finite word widths, while avoiding the loss of most significant bits. The technique is applica... | 02/07/2006 |
| 6993195 | Coding and noise filtering an image sequence The invention provides a method of and a device for coding (10*) an image sequence (g(i,j,k)). The device (10*) has a noise filter (12) for noise filtering (12) the image sequence (g(i,j,k)), and for regarding the noise filtering (12 | 01/31/2006 |
