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| Number | Title | Issue Date |
| 8185571 | Processor for performing multiply-add operations on packed data A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor p... | 05/22/2012 |
| 8150902 | Processing with compact arithmetic processing element A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplicat... | 04/03/2012 |
| 8010590 | Configurable arithmetic block and a method of implementing a configurable arithmetic block in a device having programmable logic A configurable arithmetic block for implementing arithmetic functions in a device having programmable logic is described. The configurable arithmetic block comprises a first plurality of registers coupled to receive input data; a second plurality of registers couple... | 08/30/2011 |
| 7853635 | Modular binary multiplier for signed and unsigned operands of variable widths A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection registe... | 12/14/2010 |
| 7509367 | Method and apparatus for performing multiply-add operations on packed data A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor p... | 03/24/2009 |
| 7430577 | Computationally efficient mathematical engine A method and system for performing many different types if algorithms utilizes a single mathematical engine such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical engine includes a selectively contr... | 09/30/2008 |
| 7424505 | Method and apparatus for performing multiply-add operations on packed data A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor p... | 09/09/2008 |
| 7395294 | Arithmetic logic unit An arithmetic logic unit is provided. The arithmetic logic unit preferably includes a minimum of routing delays. An arithmetic logic unit according to the invention preferably receives a plurality of operands from a plurality of operand registers, performs an arithm... | 07/01/2008 |
| 7359565 | Method of filtering pixels in a video encoding process A method and apparatus, particularly suited to SIMD instruction sets, to filter streaming video information encoded under a predictive encoding algorithm specified under video encoding standards, such as MPEG 4 or H.264/AVC. The filtering operation de-blocks or remo... | 04/15/2008 |
| 7353244 | Dual-multiply-accumulator operation optimized for even and odd multisample calculations According to some embodiments, a dual multiply-accumulate operation optimized for even and odd multisample calculations is disclosed. ... | 04/01/2008 |
| 7346761 | Alu with auxiliary units for pre and post processing of operands and immediate value within same instruction cycle An arithmetic and logic device as an integral part of a processing unit is provided to achieve code size and overhead reduction. The arithmetic and logic device contains several auxiliary computing units, each of which is capable of simple arithmetic and logical ope... | 03/18/2008 |
| 7343388 | Implementing crossbars and barrel shifters using multiplier-accumulator blocks An interface receiver, which is part of an interface that allows the transfer of data between two incompatible I/O standards, includes a crossbar and a barrel shifter that can be implemented using multiplier-accumulator blocks. The crossbar reorders an incoming burs... | 03/11/2008 |
| 7315879 | Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and parallel multipliers A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate core (120) also includes a plurality of Booth decoder cells (110... | 01/01/2008 |
| 7293258 | Data processor and method for using a data processor with debug circuit A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of multi-bit subfields of a vector operand independently. Debug action ... | 11/06/2007 |
| 7242325 | Error correction compensating ones or zeros string suppression An error correction compensating ones or zeros string suppression system and method for use in a digital transmission system is herein disclosed. In digital transmission systems utilizing error control coding (ECC)/forward error correction (FEC) to reduce the number... | 07/10/2007 |
| 7222112 | Engine control system using a cascaded neural network A method, system and machine-readable storage medium for monitoring an engine using a cascaded neural network that includes a plurality of neural networks is disclosed. In operation, the method, system and machine-readable storage medium store data corresponding to ... | 05/22/2007 |
| 7212959 | Method and apparatus for accumulating floating point values A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for dir... | 05/01/2007 |
| 7171535 | Serial operation pipeline, arithmetic device, arithmetic-logic circuit and operation method using the serial operation pipeline A general-purpose serial operation pipeline realizes a complicated processing flow with an extemporaneous and explosive amount of operations with respect to various data sizes. A plurality of arithmetic-logic circuits (SALCs) that are controlled individually, and th... | 01/30/2007 |
| 7143268 | Circuit and method for instruction compression and dispersal in wide-issue processors A data processor includes execution clusters, an instruction cache, an instruction issue unit, and alignment and dispersal circuitry. Each execution cluster includes an instruction execution pipeline having a number of processing stages, and each execution pipeline ... | 11/28/2006 |
| 7111155 | Digital signal processor computation core with input operand selection from operand bus for dual operations A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features... | 09/19/2006 |
| 7107305 | Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions A tightly coupled dual 16-bit multiply-accumulate (MAC) unit for performing single-instruction/multiple-data (SIMD) operations may forward an intermediate result to another operation in a pipeline to resolve an accumulating dependency penalty. The MAC unit may also ... | 09/12/2006 |
| 7100025 | Apparatus and method for performing single-instruction multiple-data instructions An apparatus and method for performing single-instruction multiple-data instructions using a single multiply-accumulate unit while minimizing operational latency. The multiply-accumulate unit generates a first half and a second half of a data result. A register stor... | 08/29/2006 |
| 7062635 | Processor system and method providing data to selected sub-units in a processor functional unit A processor (50) operable in response to an instruction set comprising a plurality of instructions. The processor comprises a functional unit (52) comprising an integer number S of sub-units (541, 542, 54... | 06/13/2006 |
| 7043519 | SIMD sum of product arithmetic method and circuit, and semiconductor integrated circuit device equipped with the SIMD sum of product arithmetic circuit In an SIMD sum of product arithmetic method of enabling a concurrent execution of 2n (where n is a natural number) parallel sum of product arithmetic (operations), the SIMD sum of product arithmetic is executed using 2m (m=0, . . . , log2 n) ac... | 05/09/2006 |
| 7027598 | Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption prot... | 04/11/2006 |
| 7027597 | Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption prot... | 04/11/2006 |
| 7017136 | Architecture and interconnect scheme for programmable logic circuits An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between l... | 03/21/2006 |
| 7013321 | Methods and apparatus for performing parallel integer multiply accumulate operations According to the invention, a processing core that executes a parallel multiply accumulate operation is disclosed. Included in the processing core are a first, second and third input operand registers; a number of functional blocks; and, an output operand register. ... | 03/14/2006 |
| 6999985 | Single instruction multiple data processing A data processing system is provided with an instruction (ADD8TO16) that unpacks non-adjacent portions of a data word using sign or zero extension and combines this with a single-instruction-multiple-data type arithmetic operation, such as an add, performed in respo... | 02/14/2006 |
| 7000097 | System and method for handling load and/or store operations in a superscalar microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose i... | 02/14/2006 |
| 6973561 | Processor pipeline stall based on data register status A method of recovering from loading invalid data into a register within a pipelined processor. The method comprises the steps of (A) setting a register status for the register to an invalid state in response to loading invalid data into the register and (B) stalling... | 12/06/2005 |
| 6957320 | System and method for handling load and/or store operations in a superscalar microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose i... | 10/18/2005 |
| 6952711 | Maximally negative signed fractional number multiplication A method and processor for multiplying two maximally negative fractional numbers to produce a 32-bit result are provided. Operands are fetched from a source location for operation of a multiplication operation. Result outputs corresponding to a maximally negative re... | 10/04/2005 |
| 6922716 | Method and apparatus for vector processing A processor includes a first vector processing unit including a first register file and first vector arithmetic logic unit; a second vector processing unit including a second register file and second vector arithmetic logic unit wherein the first register file has a... | 07/26/2005 |
| 6918024 | Address generating circuit and selection judging circuit An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the... | 07/12/2005 |
| 6912557 | Math coprocessor A math coprocessor 1300 includes a multiply-accumulate unit 1600. Multiplier-accumulate unit 1600 includes a multiplier array 1603 for selectively multiplying first and second operands, the first and second operands having a data type sel... | 06/28/2005 |
| 6904446 | Floating point multiplier/accumulator with reduced latency and method thereof A circuit (10) for multiplying two floating point operands (A and C) while adding or subtracting a third floating point operand (B) removes latency associated with normalization and rounding from a critical speed path for dependent calculations. An intermedia... | 06/07/2005 |
| 6889240 | Data processing device having a central processing unit and digital signal processing unit In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same ch... | 05/03/2005 |
| 6854003 | Video frame rendering engine A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing and animation as well as digital signal and image processing. One or more such circuits are provided on an inte... | 02/08/2005 |
| 6836147 | Function block A function block allows a multiplier and a multi-input multiplexer to be realized with a small number of blocks. A logical function generator generates a logical output signal from first to fourth logical inputs thereof according to a logical function selected from ... | 12/28/2004 |
