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| Number | Title | Issue Date |
| 8069201 | 8×8 transform and quantization Low complexity (16 bit arithmetic) video compression has 8×8 block with transforms using 8×8 integer matrices and quantization with look up table scalar plus constant right shift for all quantization steps. Inverse quantization also a look up table scalar plus rig... | 11/29/2011 |
| 7974997 | Hardware matrix computation for wireless receivers In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor ... | 07/05/2011 |
| 7895254 | Eigenvalue decomposition and singular value decomposition of matrices using Jacobi rotation Techniques for decomposing matrices using Jacobi rotation are described. Multiple iterations of Jacobi rotation are performed on a first matrix of complex values with multiple Jacobi rotation matrices of complex values to zero out the off-diagonal elements in the fi... | 02/22/2011 |
| 7849126 | System and method for fast matrix factorization The Present invention provides a system and method for fast computing the Cholesky factorization of a positive definite matrix. In order to reduce the computation time of matrix factorizations, the present invention uses three atomic components, namely MA atoms, M a... | 12/07/2010 |
| 7725520 | Processor The present invention provides a processor including data manipulating means for generating an arbitrary combination of elements of a first input vector and elements of a second input vector, arithmetic means for performing a product-sum operation on the combination... | 05/25/2010 |
| 7571203 | Processing device for a pseudo inverse matrix and V-BLAST system Disclosed is a V-BLAST system for a MIMO communication system. In the V-BLAST system for a MIMO communication system, a pseudo inverse matrix calculator receives a channel transfer function matrix including channel information and produces a cofactor matrix a... | 08/04/2009 |
| 7490120 | Method and structure for producing high performance linear algebra routines using a selectable one of six possible level 3 L1 kernel routines A method (and structure) for improving at least one of speed and efficiency when executing level 3 dense linear algebra subroutines on a computer. An optimal matrix subroutine is selected from among a plurality of matrix subroutines stored in a memory that could alt... | 02/10/2009 |
| 7487195 | Method and structure for producing high performance linear algebra routines using composite blocking based on L1 cache size A method (and structure) for performing a matrix subroutine, includes storing data for a matrix subroutine call in a computer memory in an increment block size that is based on a cache size. ... | 02/03/2009 |
| 7469266 | Method and structure for producing high performance linear algebra routines using register block data format routines A method (and structure) of executing a matrix operation, includes, for a matrix A, separating the matrix A into blocks, each block having a size p-by-q. The blocks of size p-by-q are then stored in a cache or memory in at least one of the two following ways. The el... | 12/23/2008 |
| 7454454 | Method and apparatus for efficient calculation of a matrix power series The present invention provides a method and system for computing a matrix power series according to one embodiment of the present invention. Memory structures for storing a partial sum, current and previous series terms are allocated. First and second pointers are a... | 11/18/2008 |
| 7386582 | Method and structure for producing high performance linear algebra routines using a hybrid full-packed storage format A method (and structure) of linear algebra processing, including processing a matrix data of a triangular packed format matrix in at least one matrix subroutine designed to process matrix data in a full format, using a hybrid full-packed data structure that provides... | 06/10/2008 |
| 7373369 | Advanced execution of extended floating-point add operations in a narrow dataflow A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the ... | 05/13/2008 |
| 7370264 | H-matrix for error correcting circuitry A matrix H for encoding data words is defined for wide word ECC with uniform density and a reduced number of components. The H-matrix is incorporated in an encode unit operable to Hamming encode a data word with a 10×528 matrix generated in groups of four columns w... | 05/06/2008 |
| 7363200 | Apparatus and method for isolating noise effects in a signal A matrix includes samples associated with a first signal and samples associated with a second signal. The second signal includes a first portion associated with the first signal and a second portion associated with at least one disturbance, such as white noise or co... | 04/22/2008 |
| 7359929 | Fast solution of integral equations representing wave propagation A technique for solving a set of wave equations in a region uses points arranged in a grid spanning the region or coefficients of wave expansion for objects located in the region. The grid points or the coefficients are partitioned into blocks on multiple levels, an... | 04/15/2008 |
| 7355917 | Two-dimensional data memory A two-dimensional data memory (1) comprising memory elements which are arranged in rows and columns, which are designed to store in each case one data word, which in the row direction and in the column direction are coupled locally to their respectively adjac... | 04/08/2008 |
| 7337205 | Matrix multiplication in a vector processing system To perform multiplication of matrices in a vector processing system, partial products are obtained by dot multiplication of vector registers containing multiple copies of elements of a first matrix and vector registers containing values from rows of a second matrix.... | 02/26/2008 |
| 7333530 | Despread signal recovery in digital signal processors A digital signal processor performs despread decoding in wireless telephone systems. Orthogonal codes are used to combine data signals into one overall coded signal which is transmitted. The orthogonal codes are used to retrieve individual data signals from the tran... | 02/19/2008 |
| 7330864 | System and method for using native floating point microprocessor instructions to manipulate 16-bit floating point data representations A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction set. The method contemplates the use a variety of techniques for conver... | 02/12/2008 |
| 7321914 | Fast method for calculating powers of two as a floating point data type A computing system is adapted to calculate an exponent portion of a floating point data type, and is preferably employed in calculating powers of two in a computer language processing environment supporting a union declaration functionality and a left shift function... | 01/22/2008 |
| 7313788 | Vectorization in a SIMdD DSP architecture A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access pattern of data required for implementing the loop in the architecture... | 12/25/2007 |
| 7296048 | Semiconductor circuit for arithmetic processing and arithmetic processing method There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for ... | 11/13/2007 |
| 7280985 | Logic arrangement, data structure, system and method for multilinear representation of multimodal data ensembles for synthesis, recognition and compression A data structure, method, storage medium and logic arrangement are provided for use in collecting and analyzing multilinear data describing various characteristics of different objects. In particular it is possible to recognize an unknown individual, an unknown obje... | 10/09/2007 |
| 7263191 | Method and apparatus for encrypting data A method for encrypting data comprising dividing a first data set into a second data set and a third data set; deriving a first value using the second data set as an input into a polynomial equation; deriving a second value using the third data set as an input into ... | 08/28/2007 |
| 7240082 | Method for processing efficiency in a pipeline architecture A method for improved processing efficiency of pipeline architecture with a processor. The processor has a first functional unit; a second functional unit; and a control unit electrically connected to the first and the second functional units for generating a plural... | 07/03/2007 |
| 7236998 | System and method for solving a large system of dense linear equations A method and system for solving a large system of dense linear equations using a system having a processing unit and one or more secondary processing units that can access a common memory for sharing data. A set of coefficients corresponding to a system of linear eq... | 06/26/2007 |
| 7219212 | Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maint... | 05/15/2007 |
| 7219119 | Procedure for computing the Cholesky decomposition in a parallel multiprocessor system The invention relates to a procedure for computing the Cholesky decomposition of a positive definite matrix into a product of a lower and an upper triagonal matrix having a dimension of L in a multi-channel procedure, wherein: the ... | 05/15/2007 |
| 7215726 | Method for interference suppression for TDMA -and/or FDMA transmission A method for interference suppression for TDMA and/or FDMA transmission, which at least approximately can be described as pulse amplitude modulation, with an arbitrary number of receive antennas. The method comprises filtering of at least one complex-valued received... | 05/08/2007 |
| 7216140 | Efficient implementation of n-point DCT, n-point IDCT, SA-DCT and SA-IDCT algorithms An efficient implementation of n-point discrete cosine transform, n-point inverse discrete cosine transform, shape adaptive discrete cosine transform and shape adaptive inverse discrete cosine transform algorithms for multimedia compression and decompression optimiz... | 05/08/2007 |
| 7210128 | Event-driven observability enhanced coverage analysis A method for event-driven observability enhanced coverage analysis of a program parses a program into variables and data dependencies, wherein the data dependencies comprise assignments and operations. The method builds a data structure having multiple records, with... | 04/24/2007 |
| 7200631 | Method and apparatus for determining an inverse square root of a given positive-definite hermitian matrix Generally, a method and apparatus are provided for computing a matrix inverse square root of a given positive-definite Hermitian matrix, K. The disclosed technique for computing an inverse square root of a matrix may be implemented, for example, by the noise whitene... | 04/03/2007 |
| 7196708 | Parallel vector processing A video platform architecture provides video processing using parallel vector processing. The video platform architecture includes a plurality of video processing modules, each module including a plurality of processing elements (PEs). Each PE provides parallel vect... | 03/27/2007 |
| 7191378 | Method and system for providing low density parity check (LDPC) encoding An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The informati... | 03/13/2007 |
| 7184465 | Signal processing method and apparatus for a spread spectrum radio communication receiver A signal received by a base station is fed to a set of filters matched to spreading codes allocated to pilot channels originating from radio terminals. The outputs from the matched filters are processed so as to estimate parameters comprising, for each channel, eige... | 02/27/2007 |
| 7181593 | Active memory command engine and method A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also g... | 02/20/2007 |
| 7167972 | Vector/scalar system with vector unit producing scalar result from vector results according to modifier in vector instruction Described herein is a processor for executing instructions and a method therefor. The processor comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value ... | 01/23/2007 |
| 7139290 | Transmitting data into a memory cell array A method for transmitting a data stream from a circuit unit to a memory cell array includes receiving the data stream and demultiplexing it in response to a control signal, thereby dividing the data stream into a storage data stream and a mask data stream. The stora... | 11/21/2006 |
| 7137005 | Method of watermarking digital data A method of introducing a non-perceptional signal (watermark) to a digital media data is disclosed. The method is based on the representation of source digital data using a special matrix, insertion of a digital watermark into the special matrix to receive the water... | 11/14/2006 |
| 7134031 | Performance control within a multi-processor system A multi-processing system 2 measures the degree of parallelism achieved in executing program instructions and uses this to dynamically control the clock speeds and supply voltage levels applied to different processor cores 4, 6 so as to reduce the over... | 11/07/2006 |
