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| Number | Title | Issue Date |
| 7366749 | Floating point adder with embedded status information A system for providing a floating point sum includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data ... | 04/29/2008 |
| 7363337 | Floating point divider with embedded status information A system for providing floating point division includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and da... | 04/22/2008 |
| 7340592 | Executing a translated block of instructions and branching to correction code when expected top of stack does not match actual top of stack to adjust stack at execution time to continue executing without restarting translating A method of generating an expected TOS during translation of instructions. The method includes translating a first block of instructions executable in a first processor architecture, into a translated first block of instructions executable in a second processor arch... | 03/04/2008 |
| 7254696 | Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit th... | 08/07/2007 |
| 7236999 | Methods and systems for computing the quotient of floating-point intervals Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a second input interval upper-point, a first input interval upper-point, and... | 06/26/2007 |
| 7219117 | Methods and systems for computing floating-point intervals Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is produced resulting from the conditional multiplication using the first ... | 05/15/2007 |
| 7191202 | Comparator unit for comparing values of floating point operands A floating point comparator circuit for comparing a plurality of floating point operands includes a plurality of analysis circuits, one for each of the floating point operands, configured to determine a format of each of the floating point operands based upon floati... | 03/13/2007 |
| 7149882 | Processor with instructions that operate on different data types stored in the same single logical register file A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical registers, a memory unit, and a decode/execution unit. The memory unit ... | 12/12/2006 |
| 7143266 | Storing immediate data of immediate instructions in a data table An efficient coding scheme is disclosed. The coding provides for the separation of immediate data from the instruction stream. A static flow analysis determines the immediate data in the program and assigns it a location for storage in a data table. The flow analysi... | 11/28/2006 |
| 7136957 | Device bandwidth management using a bus configuration multiplexer One embodiment of the invention includes a system for changing a bus configuration of a computing device. The system includes a first bus of the computing device, a second bus, and a third bus. Additionally, a multiplexing module is coupled with the first, second, a... | 11/14/2006 |
| 7133890 | Total order comparator unit for comparing values of two floating point operands A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status informati... | 11/07/2006 |
| 7085917 | Multi-pipe dispatch and execution of complex instructions in a superscalar processor In a computer system, a method and apparatus for dispatching and executing multi-cycle and complex instructions. The method results in maximum performance for such without impacting other areas in the processor such as decode, grouping or dispatch units. This invent... | 08/01/2006 |
| 7082517 | Superscalar microprocessor having multi-pipe dispatch and execution unit In a computer system for use as a symetrical multiprocessor, a superscalar microprocessor apparatus allows dispatching and executing multi-cycle and complex instructions Some control signals are generated in the dispatch unit and dispatched with the instruction to t... | 07/25/2006 |
| 7069288 | Floating point system with improved support of interval arithmetic Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One embodiment consistent with the principles of the present invention pr... | 06/27/2006 |
| 7043626 | Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming A method and apparatus for retaining flag values when an associated data value dies. A first storage circuit includes a free list for storing physical register names (PRNs) and indications indicative of whether a physical register associated with a PRN was assigned ... | 05/09/2006 |
| 7020190 | Frequency translator using a cordic phase rotator A frequency translator uses a CORDIC phase rotator coupled to a phase accumulator to translate an input signal in frequency. The CORDIC phase rotator performs required phase angle rotations of input vectors using only shift and add operations. Thus, the frequency tr... | 03/28/2006 |
| 7016928 | Floating point status information testing circuit A floating point operand testing circuit includes an analysis circuit and a result generator circuit coupled to the analysis circuit. The analysis circuit determines the status of a floating point operand based upon data within the operand. An operand buffer may sup... | 03/21/2006 |
| 6996703 | Processing device for executing virtual machine instructions A processing device comprises an instruction memory 120 for storing virtual machine instructions, such as Java byte codes. A processor 112 of the processing device comprises a predetermined microcontroller core 114 for executing native instructi... | 02/07/2006 |
| 6993549 | System and method for performing gloating point operations involving extended exponents An extended exponent floating point unit performs an extended exponent floating point operation on a plurality of operands to produce a product of the plurality of operands. The extended exponent floating point unit groups the plurality of operands into at least one... | 01/31/2006 |
| 6976050 | System and method for extracting the high part of a floating point operand A method and system determine a high part of a floating point operand. Exponent field bits and fraction field bits of a result are set to a zero if the determined format is an infinity format or an overflow format. The exponent field bits and the fraction field bits... | 12/13/2005 |
| 6970898 | System and method for forcing floating point status information to selected values A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or more control input signals, determines one or more predetermined for... | 11/29/2005 |
| 6961841 | Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors (“MAP”) in the memory subsystem. The MAP may comprise one or more field programmable gate arrays (“FPGAs”) which function to perform identif... | 11/01/2005 |
| 6961744 | System and method for generating an integer part of a logarithm of a floating point operand A logarithm unit computes an integer part of a logarithm of a floating point operand according to an embodiment of the present invention. The logarithm unit analyzes a format of the floating point operand and generates at least one signal representative of the forma... | 11/01/2005 |
| 6961846 | Data processing unit, microprocessor, and method for performing an instruction The present invention relates to a data processing unit for executing instructions stored in a memory comprising a plurality of registers coupled with an execution unit comprising a logic unit for execution of logic operations. The logic unit comprises a first logic... | 11/01/2005 |
| 6957320 | System and method for handling load and/or store operations in a superscalar microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose i... | 10/18/2005 |
| 6937757 | Implementation and uses of XsRGB An extended colorspace which has a higher accuracy and a wider gamut than sRGB color space is disclosed. The extended color space includes an alpha channel which defines the translucency of the color image. The alpha channel is different from known alpha channels in... | 08/30/2005 |
| 6934828 | Decoupling floating point linear address A technique is described to reduce the complexity of floating point linear address (FLA) maintenance in a superscalar processor by coupling FLA updates when floating point data is stored instead of when floating point addresses are stored. ... | 08/23/2005 |
| 6912173 | Method and system for fast memory access An address device simultaneously provides a first address to a first memory section using a first address bus and a second, incrementally higher, address to a second memory section using a second address bus. A buffer can then read from or write to the first and sec... | 06/28/2005 |
| 6792443 | Economical on-the-fly rounding for digit-recurrence algorithms Apparatus and methods are provided for an improved on-the-fly rounding technique for digit-recurrence algorithms, such as division and square root calculations. According to one embodiment, only two forms of an intermediate result of an operation to be performed by ... | 09/14/2004 |
| 6405305 | Rapid execution of floating point load control word instructions A microprocessor with a floating point unit configured to rapidly execute floating point load control word (FLDCW) type instructions in an out of program order context is disclosed. The floating point unit is configured to schedule instructions older than... | 06/11/2002 |
| 6289365 | System and method for floating-point computation A system is disclosed for performing floating point computation in connection with numbers in a base floating point representation (such as the representation defined in IEEE Std. 754) that defines a plurality of formats, including a normalized format and... | 09/11/2001 |
| 6233672 | Piping rounding mode bits with floating point instructions to eliminate serialization A floating point unit is provided which conveys the rounding mode in effect upon dispatch of a particular instruction with that particular instruction into the execution pipeline of the floating point unit. Upon dispatch of a control word update instructi... | 05/15/2001 |
| 6141670 | Apparatus and method useful for evaluating periodic functions A computer and a method of using the computer to reduce an original argument to obtain a periodic function of the argument. A special number Pj is employed that is close to a nontrivial even-integral multiple π. The technique subtracts a non-n... | 10/31/2000 |
| 6134573 | Apparatus and method for absolute floating point register addressing An apparatus and method for improving the execution of floating point instructions in a microprocessor is provided. During decode of a floating point instruction, translation logic generates absolute addresses of specified registers in a floating point re... | 10/17/2000 |
| 6131106 | System and method for floating-point computation for numbers in delimited floating point representation Floating point numbers and other values are represented in a "delimited" representation in which all numbers, including those which would in the IEEE Std. 754 representation, be in the de-normalized format, are in a format which is normalized with an impl... | 10/10/2000 |
| 6105047 | Method and apparatus for trading performance for precision when processing denormal numbers in a computer system An apparatus to improve the speed of handling of denormal numbers in a computer system, the apparatus comprising a mode bit and a selector, the mode bit set when denormals are to be replaced by zero, the selector having a first input and an output, the fi... | 08/15/2000 |
| 6029243 | Floating-point processor with operand-format precision greater than execution precision A floating-point processor nominally capable of single and double, but not extended, precision execution stores operands in extended-precision format. A format converter converts single and double precision source values to extended-precision format. Trap... | 02/22/2000 |
| 6021422 | Partitioning of binary quad word format multiply instruction on S/390 processor There is a unique partitioning problem in determining how to execute the floating point multiply instruction defined by IEEE 754 standard for the quad word format on a S/390 processor. Several manufacturers including IBM and HP define the binary quad word... | 02/01/2000 |
| 5886915 | Method and apparatus for trading performance for precision when processing denormal numbers in a computer system An apparatus to improve the speed of handling of denormal numbers in a computer system, the apparatus comprising a mode bit and a selector, the mode bit set when denormals are to be replaced by zero, the selector having a first input and an output, the fi... | 03/23/1999 |
| 5761105 | Reservation station including addressable constant store for a floating point processing unit A reservation station with an addressable constant store enables the provision of floating point constants to arithmetic units in a floating point unit of a superscalar processor. Floating point constant identifiers supplied with floating point instructio... | 06/02/1998 |
