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| Number | Title | Issue Date |
| 8185570 | Three-term input floating-point adder-subtractor The adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a man... | 05/22/2012 |
| 8161091 | Method for performing decimal floating point addition A method for performing a decimal floating point operation including receiving a first operand having a first coefficient and a first exponent into a first register. A second operand having a second coefficient and a second exponent are received into a second regist... | 04/17/2012 |
| 8161090 | Floating-point fused add-subtract unit In a particular embodiment, a method is disclosed that includes receiving first and second operands at a floating-point fused add-subtract circuit. The method further includes simultaneously performing add and subtract operations on the first and second operands via... | 04/17/2012 |
| 8131795 | High speed adder design for a multiply-add based floating point unit A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The... | 03/06/2012 |
| 8060549 | Method and apparatus for accumulating floating point values A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for dir... | 11/15/2011 |
| 8046400 | Apparatus and method for optimizing the performance of x87 floating point addition instructions in a microprocessor A microprocessor having a Precision Control (PC) field, an instruction dispatcher, and a Floating Point unit (FPU). The FPU receives an FP Add instruction from the instruction dispatcher, and generates a sum from its addends. The FPU determines whether any condition... | 10/25/2011 |
| 7991817 | Method and a circuit using an associative calculator for calculating a sequence of non-associative operations An apparatus and method that use an associative calculator for calculating a sequence of non-associative operations on a set of input data, comprising: using the associative calculator to calculate from the set of input data an evaluated value of each operation of s... | 08/02/2011 |
| 7873688 | Processing method and computer system for summation of floating point data A computer system execute summation processing even if the computing sequence is not adhered to in a system for computing a sum of floating point data of a plurality of nodes. Each node sends floating point data to a reduction mechanism, and the reduction mechanism ... | 01/18/2011 |
| 7707236 | Methods and apparatus for an efficient floating point ALU The present invention provides an improved technique for performing a near processing path exponent difference in an arithmetic logic unit (ALU) of a microprocessor. In one embodiment, an apparatus having a separate logic circuit for near processing path and far pro... | 04/27/2010 |
| 7552165 | Method and system to implement an improved floating point adder with integrated adding and rounding Systems and methods to implement an improved floating point adder are presented. The adder integrates adding and rounding. According to an exemplary method, of adding two floating point numbers together, a first mantissa, a second mantissa, and an input bit are adde... | 06/23/2009 |
| 7546328 | Decimal floating-point adder A decimal floating-point adder is described that performs addition and subtraction on decimal floating-point operands. The decimal floating-point adder includes an alignment unit that receives a first floating-point number and a second floating-point number, and ali... | 06/09/2009 |
| 7519645 | System and method for performing decimal floating point addition A method for performing a decimal floating point operation. A first operand including a first coefficient and a first exponent is received. The method also includes receiving a second operand that includes a second coefficient and a second exponent. An operation ass... | 04/14/2009 |
| 7490119 | High speed adder design for a multiply-add based floating point unit An apparatus and computer program product are provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and s... | 02/10/2009 |
| 7475104 | System and method for providing a double adder for decimal floating point operations A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding... | 01/06/2009 |
| 7469265 | Methods and apparatus for performing multi-value range checks In a first aspect, a method is provided for determining in which of n intervals a sum of two or more numbers resides. The method includes determining the two or more numbers, and providing fewer than n compress circuits each adapted to (1) input the two or more numb... | 12/23/2008 |
| 7437400 | Data processing apparatus and method for performing floating point addition A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic for determining which of the first and second floati... | 10/14/2008 |
| 7433911 | Data processing apparatus and method for performing floating point addition A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic operable to determine the larger operand of the firs... | 10/07/2008 |
| 7392274 | Multi-function floating point arithmetic pipeline A scalable engine having multiple datapaths, each of which is a unique multi-function floating point pipeline capable of performing a four component dot product on data in a single pass through the datapath, which allows matrix transformations to be computed in an e... | 06/24/2008 |
| 7373369 | Advanced execution of extended floating-point add operations in a narrow dataflow A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the ... | 05/13/2008 |
| 7373489 | Apparatus and method for floating-point exception prediction and recovery An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction... | 05/13/2008 |
| 7366749 | Floating point adder with embedded status information A system for providing a floating point sum includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data ... | 04/29/2008 |
| 7356553 | Data processing apparatus and method for determining a processing path to perform a data processing operation on input data elements The present invention provides a data processing apparatus and method for performing a data processing operation on first and second floating point data elements, the first floating point data element specifying a first exponent and the second floating point data el... | 04/08/2008 |
| 7356554 | Variable fixed multipliers using memory blocks A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the... | 04/08/2008 |
| 7346644 | Devices and methods with programmable logic and digital signal processing regions A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly i... | 03/18/2008 |
| 7337202 | Shift-and-negate unit within a fused multiply-adder circuit A low-power shift-and-negate unit within a fused multiply-adder circuit is disclosed. The shift-and-negate unit includes a large shift stage, a coarse shift stage, a negate stage and a fine shift stage. The large shift stage receives a first set of shift signals and... | 02/26/2008 |
| 7322032 | Methods and apparatus for scheduling operation of a data source A computerized device has dynamically modifiable hardware, such as an ASIC, that performs queue-scheduling operations. The hardware incorporates a generic sorting processor (GSP) that is dynamically configurable to implement various sorting algorithms to meet specif... | 01/22/2008 |
| 7320013 | Method and apparatus for aligning operands for a processor A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second opera... | 01/15/2008 |
| 7263539 | Circuit and method for generating fixed point data with reduced circuit scale A decoding rate is improved while reducing a circuit scale, in a fixed point data generating circuit. When a plurality of floating point data are inputted, for example, the maximum floating point data is detected as a reference data among the plurality of floating p... | 08/28/2007 |
| 7197625 | Alignment and ordering of vector elements for single instruction multiple data processing The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit int... | 03/27/2007 |
| 7164290 | Field programmable gate array logic unit and its cluster The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate un... | 01/16/2007 |
| 7149765 | Apparatus and method for precision binary numbers and numerical operations An method and/or apparatus for representing and/or operating on numerical values in binary systems whereby numerical values having integer and fractional portions are stored in non-contiguous memory locations. ... | 12/12/2006 |
| 7142325 | Document management device, communications terminal device, document management program, communications control program and document management system A document management device obtains thumbnail information as to a requested document out of an image transmitted via a public network, judges as to whether the thumbnail information is correct with respect to the requested document, and returns the requested docume... | 11/28/2006 |
| 7119576 | Devices and methods with programmable logic and digital signal processing regions A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least helping to perform digital signal processing tasks that are unduly i... | 10/10/2006 |
| 7099910 | Partitioned shifter for single instruction stream multiple data stream (SIMD) operations A method of enabling a single instruction stream multiple data stream operation and a double precision floating point operation within a single floating point execution unit which includes providing a floating point unit with a two way aligner and a two way normaliz... | 08/29/2006 |
| 7085421 | Image processing method for facilitating data transmission An image processing method for facilitating data transmission is provided. An image compression method is performed to convert X-bits binary digital signals to a binary compressed data in a floating-point form of (1.n)*2m. Bit m represents the first bit w... | 08/01/2006 |
| 7062635 | Processor system and method providing data to selected sub-units in a processor functional unit A processor (50) operable in response to an instruction set comprising a plurality of instructions. The processor comprises a functional unit (52) comprising an integer number S of sub-units (541, 542, 54... | 06/13/2006 |
| 7061268 | Initializing a carry chain in a programmable logic device A logic circuit includes a first series of logic elements. Each logic element has a look-up table (LUT) and a dedicated adder to implement an arithmetic mode in the logic element. The logic circuit also includes a carry chain connecting the first series of logic ele... | 06/13/2006 |
| 7054898 | Elimination of end-around-carry critical path in floating point add/subtract execution unit A processor having a floating point execution unit with improved parallelism in the adder (add/subtract) unit is disclosed. A preferred aspect of the invention is a new use of the compare logic in the floating point execution unit, coupled with an end-around-carry b... | 05/30/2006 |
| 7043516 | Reduction of add-pipe logic by operand offset shift The shifters (30, 32) that a floating-point processor (10)'s addition pipeline (14) uses to align or normalize floating-point operands' mantissas before addition or subtraction shift a given mantissa pair one more bit to the left for subtraction... | 05/09/2006 |
| 7030658 | Systems and methods for operating logic circuits Systems and methods for reducing the power consumption of some combinations of logic gates by reducing the number of unnecessary transitions that are made by logic gates that do not affect the output of the logic. In one embodiment, a modified exclusive-OR (XOR) gat... | 04/18/2006 |
