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| Number | Title | Issue Date |
| 8176111 | Low latency floating-point divider An improved method and apparatus for performing floating-point division is disclosed. In a particular embodiment, fractional operands are pre-scaled and an estimate of a reciprocal of the pre-scaled fractional divisor is obtained from a lookup table using a portion ... | 05/08/2012 |
| 8166092 | Arithmetic device for performing division or square root operation of floating point number and arithmetic method therefor When division X/Y of floating point numbers is performed, bit string data of a mantissa x including a fraction xf of X or a mantissa y including a fraction yf of Y is shifted in accordance with magnitude relation between them to perform a fraction computation. There... | 04/24/2012 |
| 7873687 | Method for calculating a result of a division with a floating point unit with fused multiply-add The invention proposes a Floating Point Unit with fused multiply-add, with one addend Method for calculating a result of a division with an A-register and a B-register for two multiplicand operands and a C-register for an addend operand, wherein a divide processor u... | 01/18/2011 |
| 7752250 | Rounding floating point division results A method for determining the correct result and the correct guard and sticky bits to obtain a more accurate result in floating point divide operations is presented. An intermediate divide result or quotient is obtained from a multiply-add hardware pipeline of a floa... | 07/06/2010 |
| 7613762 | Floating point remainder with embedded status information A system for providing a floating point remainder comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand an... | 11/03/2009 |
| 7539720 | Low latency integer divider and integration with floating point divider and method A method and device divides a dividend by a divisor, the dividend and the divisor both being integers. The method and device determine a maximum possible number of quotient digits (NDQ) based on a number of significant digits of the divisor and the dividend, normali... | 05/26/2009 |
| 7467174 | Processing unit having decimal floating-point divider using Newton-Raphson iteration A decimal floating-point divider is described that implements efficient hardware-based techniques for performing decimal floating-point division. The divider uses an accurate piecewise linear approximation to obtain an initial estimate of a divisor's reciprocal. The... | 12/16/2008 |
| 7363337 | Floating point divider with embedded status information A system for providing floating point division includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and da... | 04/22/2008 |
| 7321916 | Methods and apparatus for extracting integer remainders Methods and apparatus for determining a remainder value are disclosed. The methods and apparatus extract a residuary subset bitfield value from a binary value that is calculated using a scaled approximate reciprocal value that is associated with a compound exponent ... | 01/22/2008 |
| 7236999 | Methods and systems for computing the quotient of floating-point intervals Computing an output interval includes producing a first result from a conditional selection using a first operand, a second operand, and a third operand, the operands respectively including a second input interval upper-point, a first input interval upper-point, and... | 06/26/2007 |
| 7222146 | Method and apparatus for facilitating exception-free arithmetic in a computer system One embodiment of the present invention provides a system that facilitates performing exception-free arithmetic operations within a computer system. During execution of a computer program, the system receives an instruction to perform an arithmetic operation that in... | 05/22/2007 |
| 7194499 | Pipelined divider and dividing method with small lookup table A pipelined divider with a small lookup table is disclosed. The pipelined divider can greatly reduce the size of a lookup table with a low cost to overcome the problems involved in the conventional pipelined divider requiring a large lookup table due to its iterativ... | 03/20/2007 |
| 7167891 | Narrow data path for very high radix division Methods, machines, and systems are provided for very high radix division using narrow data paths. A numerator and denominator are received for a very high radix division calculation. An approximate reciprocal of the denominator is obtained from a data structure. The... | 01/23/2007 |
| 7167887 | Circuitry for carrying out square root and division operations The invention provides circuitry for carrying out a square root operation and a division operation. The circuitry utilizes common iteration circuitry for carrying out a plurality of iterations and means for identifying if an square root operation or a division opera... | 01/23/2007 |
| 7127483 | Method and system of a microprocessor subtraction-division floating point divider The specification discloses a structure of and a method of operating a subtractive division (SD) cell where a portion of the partial remainder or estimated partial remainder directly indicates the next quotient digit. More particularly, by sufficiently constraining ... | 10/24/2006 |
| 7113593 | Recursive cryptoaccelerator and recursive VHDL design of logic circuits A method and apparatus for performing cryptographic computations employing recursive algorithms to accelerate multiplication and squaring operations. Products and squares of long integer values are recursively reduced to a combination of products and squares reduced... | 09/26/2006 |
| 7071935 | Graphics system with just-in-time decompression of compressed graphics data A graphics system and method for increasing efficiency of decompressing blocks of compressed geometry data and reducing redundant transformation and lighting calculations is disclosed. Multiple decompression pipelines are used to increases the decompression speed. A... | 07/04/2006 |
| 7069288 | Floating point system with improved support of interval arithmetic Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One embodiment consistent with the principles of the present invention pr... | 06/27/2006 |
| 7069289 | Floating point unit for detecting and representing inexact computations without flags or traps A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a sep... | 06/27/2006 |
| 7054898 | Elimination of end-around-carry critical path in floating point add/subtract execution unit A processor having a floating point execution unit with improved parallelism in the adder (add/subtract) unit is disclosed. A preferred aspect of the invention is a new use of the compare logic in the floating point execution unit, coupled with an end-around-carry b... | 05/30/2006 |
| 7039666 | Circuitry for carrying out at least one of a square root and a division operation The invention provides circuitry for carrying out at least one of a square root operation and a division operation. The circuitry utilizes a carry slave adder and a carry propagate adder part. The carry save adder and the carry propagate adder part are arranged in p... | 05/02/2006 |
| 7027597 | Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption prot... | 04/11/2006 |
| 7027598 | Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption prot... | 04/11/2006 |
| 7013320 | Apparatus and method for remainder calculation using short approximate floating-point quotient An apparatus and method for creating lookup tables of approximate floating-point quotients which exactly represent the underlying value, within the range of the specified precision. The lookup tables are created without any extraneous data beyond what is needed and ... | 03/14/2006 |
| 6970525 | High-speed, high granularity baud clock generation A baud clock (15) for use by a serial communication interface (67) is generated by dividing a base clock of the serial communication interface by one of a plurality of possible composite divisors (DEG). Each composite divisor is indicative o... | 11/29/2005 |
| 6963895 | Floating point pipeline method and circuit for fast inverse square root calculations Methods and systems are provided for fast computation of reciprocal square root for floating-point numbers. A piece-wise linear approximation of the result mantissa is computed in two cycles and used as the input to an iteration sequence that converges cubically. Th... | 11/08/2005 |
| 6941334 | Higher precision divide and square root approximations A floating point unit includes a multiplier, an approximation circuit, and a control circuit coupled to the multiplier and the approximation circuit. The approximation circuit is configured to generate an approximation of a difference of the first result from the mu... | 09/06/2005 |
| 6922714 | Floating point unit power reduction scheme A system and method for reducing the power consumption of a floating point unit of a processor wherein the processor iteratively performs floating point calculations based upon one or more input operands. The exponential value of a floating point is precalculated wi... | 07/26/2005 |
| 6901503 | Data processing circuits and interfaces An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processo... | 05/31/2005 |
| 6847985 | Floating point divide and square root processor An iterative mantissa calculator calculates a quotient mantissa for a divide mode or a result mantissa for a square-root mode. The calculator includes at least first and second summing devices. In the divide mode, each summing device calculates a respective estimate... | 01/25/2005 |
| 6792443 | Economical on-the-fly rounding for digit-recurrence algorithms Apparatus and methods are provided for an improved on-the-fly rounding technique for digit-recurrence algorithms, such as division and square root calculations. According to one embodiment, only two forms of an intermediate result of an operation to be performed by ... | 09/14/2004 |
| 6782405 | Method and apparatus for performing division and square root functions using a multiplier and a multipartite table The division and square root systems include a multiplier. The systems also include a multipartite table system, a folding inverter, and a complement inverter, each coupled to the multiplier. The division and square root functions can be performed using three scalin... | 08/24/2004 |
| 6658444 | Method and apparatus for performing a mask-driven interval division operation One embodiment of the present invention provides a system for performing a division operation between arithmetic intervals within a computer system. The system operates by receiving interval operands, including a first interval and a second interval, wher... | 12/02/2003 |
| 6594681 | Quotient digit selection logic for floating point division/square root Quotient digit selection logic using a three-bit carry propagate adder is presented. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact. The enhanced quotient digit selection ... | 07/15/2003 |
| 6487575 | Early completion of iterative division A multiplier configured to execute division and square root operations by executing iterative multiplication operations is disclosed. The multiplier is configured to complete divide-by-two and zero dividend instructions in fewer clock cycles by detecting ... | 11/26/2002 |
| 6351760 | Division unit in a processor using a piece-wise quadratic approximation technique A computation unit computes a division operation Y/X by determining the value of a divisor reciprocal 1/X and multiplying the reciprocal by a numerator Y. The reciprocal 1/X value is determined using a quadratic approximation having a form: Ax2... | 02/26/2002 |
| 6128639 | Array address and loop alignment calculations Division system and method support a hardware division address centrifuge to provide a flexible addressing scheme, and thus facilitates the reorganization and redistribution of data between remote and local memory blocks in a distributed memory massively ... | 10/03/2000 |
| 6122651 | Method and apparatus for performing overshifted rotate through carry instructions by shifting in opposite directions Disclosed is a method and circuit for executing an overshifted rotate through carry instruction. The circuit and method generates an n-bit output operand and output carry flag which represents a result of rotating a combination of a first n-bit operand an... | 09/19/2000 |
| 5999961 | Parallel prefix operations in asynchronous processors A circuit for performing prefix computation in an asynchronous digital processor by implementing a serial process and a tree process for the same prefix computation in parallel. The first output from either processes is selected and used for the subsequen... | 12/07/1999 |
| 5954789 | Quotient digit selection logic for floating point division/square root Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exac... | 09/21/1999 |
