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| Number | Title | Issue Date |
| 8015228 | Data processing apparatus and method for performing a reciprocal operation on an input value to produce a result value A data processing apparatus and method are provided for performing a reciprocal operation on an input value d to produce a result value X. The reciprocal operation involves iterative execution of a refinement step to converge on the result value, the refinement step... | 09/06/2011 |
| 7899859 | Efficient error-check and exact-check for Newton-Raphson divide and square-root operations One embodiment of the present invention provides a system that performs both error-check and exact-check operations for a Newton-Raphson divide or square-root computation. During operation, the system performs Newton-Raphson iterations followed by a multiply for a d... | 03/01/2011 |
| 7747667 | Data processing apparatus and method for determining an initial estimate of a result value of a reciprocal operation A data processing apparatus and method generate an initial estimate of a result value that would be produced by performing a reciprocal operation on an input value. The input value and the result value are either fixed point values or floating point values. The data... | 06/29/2010 |
| 7634527 | Reciprocal estimate computation methods and apparatus In a first aspect, a first method of reciprocal estimate computation using floating point pipeline logic is provided. The first method includes the steps of (1) receiving an input value having an exponent and a mantissa when represented as a floating point number on... | 12/15/2009 |
| 7406589 | Processor having efficient function estimate instructions High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instr... | 07/29/2008 |
| 7372461 | Image processing apparatus and method of same An image processing apparatus able to decrease the number of minute unit graphics, able to achieve an improvement of performance of graphics drawing processing, and able to efficiently generate images, provided with a triangle generator for receiving vertex data fro... | 05/13/2008 |
| 7366748 | Methods and apparatus for fast argument reduction in a computing system There is disclosed method, software and apparatus for evaluating a function f in a computing device using a reduction, core approximation and final reconstruction stage. According to one embodiment of the invention, an argument reduction stage uses an approximate re... | 04/29/2008 |
| 7330864 | System and method for using native floating point microprocessor instructions to manipulate 16-bit floating point data representations A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction set. The method contemplates the use a variety of techniques for conver... | 02/12/2008 |
| 7313584 | Increased precision in the computation of a reciprocal square root A method and arrangements for increased precision in the computation of a reciprocal square root is disclosed. In accordance with the present invention, it is possible to achieve fifty three (53) bits of precision in less processing time than previously possible. | 12/25/2007 |
| 7266578 | Method and hardware for computing reciprocal square root and program for the same A reciprocal square root for a radix of x is calculated when S[j] represents the partial result obtained after j iterations of calculation, W[j], a residual, and P[j], the product of an operand X and the S[j]. Firstly, appropriate values are set to the... | 09/04/2007 |
| 7212959 | Method and apparatus for accumulating floating point values A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for dir... | 05/01/2007 |
| 7124161 | Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, ... | 10/17/2006 |
| 7117238 | Method and system for performing pipelined reciprocal and reciprocal square root operations A pipelined circuit configured to generate a Taylor's series approximation at least one function, preferably at least one of the reciprocal and the reciprocal square root, of an input value. The circuit is preloaded with or configured to generate a predetermined set... | 10/03/2006 |
| 7110463 | Efficient computation of spatial filter matrices for steering transmit diversity in a MIMO communication system Techniques for efficiently computing spatial filter matrices are described. The channel response matrices for a MIMO channel may be highly correlated if the channel is relatively static over a range of transmission spans. In this case, an initial spatial filter matr... | 09/19/2006 |
| 7099911 | Givens rotations computation A Givens rotation computation technique is provided that makes use of polynomial approximations of an expression that contains a square root function. The polynomial approximation uses polynomial coefficients that are specifically adapted to respective ones of a num... | 08/29/2006 |
| 7089159 | Method and apparatus for matrix reordering and electronic circuit simulation A matrix reordering method performs reordering of elements of a coefficient matrix created based on coefficients of linear simultaneous equations whose solutions are to be produced by parallel processing of processors of a computer in accordance with Gaussian elimin... | 08/08/2006 |
| 7080112 | Method and apparatus for computing an approximation to the reciprocal of a floating point number in IEEE format A method and apparatus allows the quick computation of an estimate of the reciprocal of a floating point number in IEEE format. A table with 2k entries allows the computation of an estimate with 2×k+3 good bits. x is a floating point number in IEEE forma... | 07/18/2006 |
| 7065546 | Method of performing quantization within a multimedia bitstream utilizing division-free instructions Methods for enhancing the performance of quantization operations by converting division operations to a combination of multiplication and shift operations, which are preferably performed on a processor supporting single-instruction multiple-data (SIMD) instructions.... | 06/20/2006 |
| 7058675 | Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, ... | 06/06/2006 |
| 7031996 | Calculating square root of binary numbers with fixed-point microprocessor A method and system is disclosed for calculating the square root of a number using a fixed-point microprocessor. The method includes employing a binary search to obtain the integer portion of the square root, and calculating a fraction of the square root utilizing t... | 04/18/2006 |
| 7027598 | Residue number system based pre-computation and dual-pass arithmetic modular operation approach to implement encryption protocols efficiently in electronic integrated circuits A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption prot... | 04/11/2006 |
| 7027597 | Pre-computation and dual-pass modular arithmetic operation approach to implement encryption protocols efficiently in electronic integrated circuits A pre-computation and dual-pass modular operation approach to implement encryption protocols efficiently in electronic integrated circuits is disclosed. An encrypted electronic message is received and another electronic message generated based on the encryption prot... | 04/11/2006 |
| 7007058 | Methods and apparatus for binary division using look-up table Improved methods of operating a digital data processor to perform binary division include estimating reciprocals of at least selected divisors based on value accessed from a look-up table. For divisors in a first numerical range, the estimation can be based on a val... | 02/28/2006 |
| 6999986 | Calculating circuit and method for computing an -th root and a reciprocal of a number A calculating circuit and a method for generating an output signal representing an output number approximating an N-th root and/or a reciprocal of an input number represented by an input signal are described. The calculating circuit includes a subtractor circuit, an... | 02/14/2006 |
| 6963895 | Floating point pipeline method and circuit for fast inverse square root calculations Methods and systems are provided for fast computation of reciprocal square root for floating-point numbers. A piece-wise linear approximation of the result mantissa is computed in two cycles and used as the input to an iteration sequence that converges cubically. Th... | 11/08/2005 |
| 6952710 | Apparatus, methods and computer program products for performing high speed division calculations The present invention provides apparatus, methods, and computer program products for non-iterative division and non-iterative reciprocal generation. In one embodiment, the present invention uses a logic network that determines the bits of the quotient of a divisor a... | 10/04/2005 |
| 6941334 | Higher precision divide and square root approximations A floating point unit includes a multiplier, an approximation circuit, and a control circuit coupled to the multiplier and the approximation circuit. The approximation circuit is configured to generate an approximation of a difference of the first result from the mu... | 09/06/2005 |
| 6920472 | Termination criteria for the interval version of Newton's method for solving systems of non-linear equations One embodiment of the present invention provides a system for finding the roots of a system of nonlinear equations within an interval vector X=(X1, . . . , Xn), wherein the system of non-linear equations is specified by a vector function ƒ=(ƒ... | 07/19/2005 |
| 6915320 | Termination criteria for the one-dimensional interval version of newton's method One embodiment of the present invention provides a system for finding zeros of a function, ƒ, within an interval, X, using the interval version of Newton's method. The system operates by receiving a representation of the interval X. This representation including a ... | 07/05/2005 |
| 6912559 | System and method for improving the accuracy of reciprocal square root operations performed by a floating-point unit The accuracy of approximating the reciprocal and the reciprocal square root of a number (N) is improved. Approximating the reciprocal of N includes: (a) estimating the reciprocal of N to produce an estimate (Xi); (b) determining a first intermediate resul... | 06/28/2005 |
| 6769006 | Method and apparatus for calculating a reciprocal A method and apparatus for the calculation of the reciprocal of a normalized mantissa M for a floating-point input number D. A formula for determining the minimum size for the look-up table in accordance with the required precision is provided, as well as formulas f... | 07/27/2004 |
| 6732134 | Handler for floating-point denormalized numbers Operations that involve denormalized numbers are handled by restructuring the input values for an operation as normalized numbers, and performing calculations on the normalized numbers. As a first step in the process of performing an operation, a determination is ma... | 05/04/2004 |
| 6665693 | Digital signal processing circuits, systems, and methods implementing approximations for a reciprocal A digital signal system (10, 100) for determining an approximate reciprocal of a value of x. The system includes an input (12) for receiving a signal, and circuitry (18) for measuring an attribute of the signal. The measured attribute relates at least in ... | 12/16/2003 |
| 6654777 | Single precision inverse square root generator A floating point inverse square root circuit is disclosed. The circuit is configured to receive a floating point value comprised of a sign bit, an exponent field, and a mantissa field. The inverse square root circuit includes a lookup table configured to ... | 11/25/2003 |
| 6601080 | Hybrid representation scheme for factor L in sparse direct matrix factorization A system that efficiently performs a CMOD operation in solving a system of equations involving a sparse coefficient matrix by identifying supernodes in the sparse matrix. Each supernode comprises a set of contiguous columns having a substantially similar ... | 07/29/2003 |
| 6581085 | Approximation circuit and method An approximation circuit approximates a function f(x) of an input value "x" by adding at least the first two terms in a Taylor series (i.e., f(a) and f'(a)(x-a)) where "a" is a number reasonably close to value "x". The first term is generated by a first l... | 06/17/2003 |
| 6553120 | Method for data decorrelation Method for the cryptography of data recorded on a medium usable by a computing unit in which the computing unit processes an input information x using a key for supplying an information F(x) encoded by a function F. The function uses a decorrelation modul... | 04/22/2003 |
| 6460063 | Division circuit and graphic display processing apparatus A division circuit which can shorten a critical path for division and can perform the division at a high speed, provided with a 1's complement processor for outputting a complement of 1 of a divisor when the divisor is negative; an adder for adding "1" to... | 10/01/2002 |
| 6385713 | Microprocessor with parallel inverse square root logic for performing graphics function on packed data elements An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executin... | 05/07/2002 |
| 6349319 | Floating point square root and reciprocal square root computation unit in a processor A method of computing a square root or a reciprocal square root of a number in a computing device uses a piece-wise quadratic approximation of the number. The square root computation uses the piece-wise quadratic approximation in the form: squareroot(X)=A... | 02/19/2002 |
