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| Number | Title | Issue Date |
| 8180822 | Method and system for processing the booth encoding 33term A computer system for computing a binary operation involving a first term multiplied by a second term resulting in a product, where the product is conditionally added to a third term in a central processing unit. The central processing unit includes a carry save add... | 05/15/2012 |
| 8166091 | Floating-point fused dot-product unit In an embodiment, a dot-product unit to perform single-precision floating-point product and addition operations is disclosed that includes a first multiplier tree unit adapted to multiply first and second significand operands to produce a first set of two partial pr... | 04/24/2012 |
| 8078660 | Bridge fused multiply-adder circuit A bridge fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The bridge fused multiply-add unit adds this functionality to existing floating-point co-processor units by including a fused multiply-add hardw... | 12/13/2011 |
| 8069200 | Apparatus and method for implementing floating point additive and shift operations A floating point (FP) shifter for use with FP adders providing a shifted FP operand as a power of the exponent base (usually two) multiplied by a FP operand. First arithmetic processor using at least one FP shifter with FP adder. FP adder for N FP operands creating ... | 11/29/2011 |
| 8051123 | Multipurpose functional unit with double-precision and filtering operations A multipurpose arithmetic functional unit selectively performs planar attribute interpolation, unary function approximation, double-precision arithmetic, and/or arbitrary filtering functions such as texture filtering, bilinear filtering, or anisotropic filtering by ... | 11/01/2011 |
| 8046399 | Fused multiply-add rounding and unfused multiply-add rounding in a single multiply-add module A computer processor including a single fused-unfused floating point multiply-add (FMA) module computes the result of the operation A*B+C for floating point numbers for fused multiply-add rounding operations and unfused multiply-add rounding operations. In one embod... | 10/25/2011 |
| 8037118 | Three-path fused multiply-adder circuit A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data... | 10/11/2011 |
| 8024393 | Processor with improved accuracy for multiply-add operations Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the int... | 09/20/2011 |
| 7912887 | Mode-based multiply-add recoding for denormal operands In a denormal support mode, the normalization circuit of a floating-point adder is used to normalize or denormalized the output of a floating-point multiplier. Each floating-point multiply instruction is speculatively converted to a multiply-add instruction, with th... | 03/22/2011 |
| 7720900 | Fused multiply add split for multiple precision arithmetic An apparatus and method for performing floating-point operations, particularly a fused multiply add operation. The apparatus includes a arithmetic logic unit adapted to produce both a high-order part (H) and a low-order part (L) of an intermediate extended result ac... | 05/18/2010 |
| 7716266 | Common shift-amount calculation for binary and hex floating point A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC an... | 05/11/2010 |
| 7543013 | Multi-stage floating-point accumulator A multi-stage floating-point accumulator includes at least two stages and is capable of operating at higher speed. In one design, the floating-point accumulator includes first and second stages. The first stage includes three operand alignment units, two multiplexer... | 06/02/2009 |
| 7509366 | Multiplier array processing system with enhanced utilization at lower precision A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of ... | 03/24/2009 |
| 7499962 | Enhanced fused multiply-add operation An apparatus, method, and system for performing an enhanced fused multiply-add operation is disclosed. In one embodiment, an apparatus includes an exponent unit. The exponent unit includes a first adder to generate S1, where S1 is the sum of an integer... | 03/03/2009 |
| 7461117 | Floating point unit with fused multiply add and method for calculating a result with a floating point unit The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) comput... | 12/02/2008 |
| 7451172 | Handling denormal floating point operands when result must be normalized A method for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. B... | 11/11/2008 |
| 7444366 | Faster shift value calculation using modified carry-lookahead adder Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input operands from three latches. A carry-lookahead adder receives the outpu... | 10/28/2008 |
| 7428566 | Multipurpose functional unit with multiply-add and format conversion pipeline A multipurpose functional unit is configurable to support a number of operations including multiply-add and format conversion operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and logical test operations. ... | 09/23/2008 |
| 7392270 | Apparatus and method for reducing the latency of sum-addressed shifters The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a b... | 06/24/2008 |
| 7392274 | Multi-function floating point arithmetic pipeline A scalable engine having multiple datapaths, each of which is a unique multi-function floating point pipeline capable of performing a four component dot product on data in a single pass through the datapath, which allows matrix transformations to be computed in an e... | 06/24/2008 |
| 7392273 | High-sticky calculation in pipelined fused multiply/add circuitry Arithmetic processing circuits in a circuit in a floating point processor having a fused multiply/ADD circuitry. In order to avoid waiting cycles in the normalizer of the floating point arithmetic, control logic calculates in an extremely early state of the overall ... | 06/24/2008 |
| 7370069 | Numerical value conversion using a look-up table for coefficient storage A device for performing numerical value conversion of a digital input value in a first unit to a second unit being a natural unit includes a look-up table storing an array of coefficients for performing the numerical value conversion. The look-up table is indexed us... | 05/06/2008 |
| 7366748 | Methods and apparatus for fast argument reduction in a computing system There is disclosed method, software and apparatus for evaluating a function f in a computing device using a reduction, core approximation and final reconstruction stage. According to one embodiment of the invention, an argument reduction stage uses an approximate re... | 04/29/2008 |
| 7352205 | Reconfigurable switching device parallel calculation of any particular algorithms A configurable architecture of a calculation device includes at least one individual configurable and/or reconfigurable switching device, whereby the output variables thereof form a time point tn-1 and the input variables of the switching device form a ti... | 04/01/2008 |
| 7353364 | Apparatus and method for sharing a functional unit execution resource among a plurality of functional units An apparatus and method for sharing a functional unit. In one embodiment, a processor may include instruction fetch logic configured to issue instructions, and a first functional unit configured to execute instructions issued from the instruction fetch logic and to ... | 04/01/2008 |
| 7353368 | Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, p... | 04/01/2008 |
| 7346643 | Processor with improved accuracy for multiply-add operations Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the int... | 03/18/2008 |
| 7320013 | Method and apparatus for aligning operands for a processor A method for transparently presenting different size operands to be processed is provided. The method initiates with providing a first operand having a first bit-width. Then, a bit width of a second operand associated with a processor is determined. The second opera... | 01/15/2008 |
| 7290023 | High performance implementation of exponent adjustment in a floating point design A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value. Exponent adjust and roundin... | 10/30/2007 |
| 7290020 | Electronic device to calculate and generate linear and non-linear functions Electronic device (10) to calculate linear functions and to calculate and generate non-linear functions, intended to process signals. The electronic device (10) is provided with a calculator unit (11) to calculate linear functions, a device (... | 10/30/2007 |
| 7254698 | Multifunction hexadecimal instructions A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructi... | 08/07/2007 |
| 7240085 | Faster shift value calculation using modified carry-lookahead adder Circuitry for reducing propagation delays in calculation of a value for use in a floating point multiply-accumulate operation. In the circuitry, a carry-save adder receives values of three input operands from three latches. A carry-lookahead adder receives the outpu... | 07/03/2007 |
| 7240204 | Scalable and unified multiplication methods and apparatus Scalable and unified multipliers for multiplication of cryptographic parameters represented as elements of either of the prime field (GF(p)) and the binary extension field (GF(2m)) include processing elements arranged to execute in pipeline stages. The pr... | 07/03/2007 |
| 7240184 | Multipurpose functional unit with multiplication pipeline, addition pipeline, addition pipeline and logical test pipeline capable of performing integer multiply-add operations A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and format conversion operations.... | 07/03/2007 |
| 7225323 | Multi-purpose floating point and integer multiply-add functional unit with multiplication-comparison test addition and exponent pipelines A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and format conversion operations.... | 05/29/2007 |
| 7225216 | Method and system for a floating point multiply-accumulator Aspects for performing a multiply-accumulate operation on floating point numbers in a single clock cycle are described. These aspects include mantissa logic for combining a mantissa portion of floating point inputs and exponent logic coupled to the mantissa logic. T... | 05/29/2007 |
| 7216139 | Programmable logic device including multipliers and configurations thereof to reduce resource utilization In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and ca... | 05/08/2007 |
| 7212959 | Method and apparatus for accumulating floating point values A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for dir... | 05/01/2007 |
| 7197625 | Alignment and ordering of vector elements for single instruction multiple data processing The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit int... | 03/27/2007 |
| 7194498 | Higher radix multiplier with simplified partial product generator A circuit and methodology for higher radix multiplication with improved partial product generation. The invention relates to the design of a high precision multiplier for an arithmetic unit of a digital processor. ... | 03/20/2007 |
