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A mouthguard includes a U-shaped upper bite plate which removably fits over upper teeth of a person, with the entire upper bite plate being made from a soft, deformable and edible gummi candy.
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| Number | Title | Issue Date |
| 8156170 | Increased precision in the computation of a reciprocal square root A method and arrangements for increased precision in the computation of a reciprocal square root is disclosed. In accordance with the present invention, it is possible to achieve fifty three (53) bits of precision in less processing time than previously possible. | 04/10/2012 |
| 7451171 | Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root operations. Exemplary embodiments include a method including receiving a first microcoded instruction in the pipeline, decoding the first microco... | 11/11/2008 |
| 7430576 | Floating point square root provider with embedded status information A system for providing a floating point square root comprises an analyzer circuit configured to determine a first status of a first floating point operand based upon data within the first floating point operand. In addition, the system comprises a results circuit co... | 09/30/2008 |
| 7406589 | Processor having efficient function estimate instructions High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instr... | 07/29/2008 |
| 7366745 | High-speed function approximation Methods and apparatuses are presented for determining coefficients for a polynomial-based approximation of a function, by iteratively estimating a first coefficient, reducing the first coefficient to a lower precision to obtain a first limited-precision coefficient,... | 04/29/2008 |
| 7353364 | Apparatus and method for sharing a functional unit execution resource among a plurality of functional units An apparatus and method for sharing a functional unit. In one embodiment, a processor may include instruction fetch logic configured to issue instructions, and a first functional unit configured to execute instructions issued from the instruction fetch logic and to ... | 04/01/2008 |
| 7346642 | Arithmetic processor utilizing multi-table look up to obtain reciprocal operands Methods for determining the square root, reciprocal square root, or reciprocal of a number performed by a processor of a computer system. The methods produce high precision estimates without using iterative steps. In addition, the methods taught herein utilize compr... | 03/18/2008 |
| 7330864 | System and method for using native floating point microprocessor instructions to manipulate 16-bit floating point data representations A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction set. The method contemplates the use a variety of techniques for conver... | 02/12/2008 |
| 7313584 | Increased precision in the computation of a reciprocal square root A method and arrangements for increased precision in the computation of a reciprocal square root is disclosed. In accordance with the present invention, it is possible to achieve fifty three (53) bits of precision in less processing time than previously possible. | 12/25/2007 |
| 7290023 | High performance implementation of exponent adjustment in a floating point design A floating point unit (FPU) which generates a correction signal and an inverted leading zero signal. Exponent logic, is configured to generate an exponent value, a first incremented exponent value, and a second incremented exponent value. Exponent adjust and roundin... | 10/30/2007 |
| 7225216 | Method and system for a floating point multiply-accumulator Aspects for performing a multiply-accumulate operation on floating point numbers in a single clock cycle are described. These aspects include mantissa logic for combining a mantissa portion of floating point inputs and exponent logic coupled to the mantissa logic. T... | 05/29/2007 |
| 7191204 | Computing system using newton-raphson method A dividing circuit and square root extracting circuit using the Newton-Raphson method. The number of places of an initial value of the Newton-Raphson method is decreased, and a part of a multiplier is omitted. Therefore the circuit scale is reduced. A circuit dedica... | 03/13/2007 |
| 7185040 | Apparatus and method for calculation of divisions and square roots Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {−1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial ... | 02/27/2007 |
| 7167887 | Circuitry for carrying out square root and division operations The invention provides circuitry for carrying out a square root operation and a division operation. The circuitry utilizes common iteration circuitry for carrying out a plurality of iterations and means for identifying if an square root operation or a division opera... | 01/23/2007 |
| 7139786 | Method and apparatus for efficiently performing a square root operation One embodiment of the present invention provides a system that performs a carry-save square root operation that calculates an approximation of a square root, Q, of a radicand, R. The system calculates Q by iteratively selecting an operation to perform based on highe... | 11/21/2006 |
| 7076516 | Efficient method of identifying non-solution or non-optimal regions of the domain of a function A method of identifying one or more regions of the domain of a function that do not contain solutions is described along with a related subdivision method. These methods may be employed in the context of branch and bound methods that use interval analysis to search ... | 07/11/2006 |
| 7039666 | Circuitry for carrying out at least one of a square root and a division operation The invention provides circuitry for carrying out at least one of a square root operation and a division operation. The circuitry utilizes a carry slave adder and a carry propagate adder part. The carry save adder and the carry propagate adder part are arranged in p... | 05/02/2006 |
| 6963895 | Floating point pipeline method and circuit for fast inverse square root calculations Methods and systems are provided for fast computation of reciprocal square root for floating-point numbers. A piece-wise linear approximation of the result mantissa is computed in two cycles and used as the input to an iteration sequence that converges cubically. Th... | 11/08/2005 |
| 6950844 | Method and apparatus for solving systems of linear inequalities One embodiment of the present invention provides a system that performs a procedure to solve a system of linear inequalities. During operation, the system receives a representation of the system of linear inequalities Ax≦b, wherein Ax≦b can be a linearized form ... | 09/27/2005 |
| 6944641 | Method for determining the square root of a long-bit number using a short-bit processor In a method for determining the square root of a long-bit number using a short-bit processor, the long-bit number is assumed to be c×22K+d, where c, d | 09/13/2005 |
| 6912559 | System and method for improving the accuracy of reciprocal square root operations performed by a floating-point unit The accuracy of approximating the reciprocal and the reciprocal square root of a number (N) is improved. Approximating the reciprocal of N includes: (a) estimating the reciprocal of N to produce an estimate (Xi); (b) determining a first intermediate resul... | 06/28/2005 |
| 6847985 | Floating point divide and square root processor An iterative mantissa calculator calculates a quotient mantissa for a divide mode or a result mantissa for a square-root mode. The calculator includes at least first and second summing devices. In the divide mode, each summing device calculates a respective estimate... | 01/25/2005 |
| 6820107 | Square root extraction circuit and floating-point square root extraction device A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output predict... | 11/16/2004 |
| 6779012 | Computer method and apparatus for division and square root operations using signed digit Computer method and apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction te... | 08/17/2004 |
| 6654777 | Single precision inverse square root generator A floating point inverse square root circuit is disclosed. The circuit is configured to receive a floating point value comprised of a sign bit, an exponent field, and a mantissa field. The inverse square root circuit includes a lookup table configured to ... | 11/25/2003 |
| 6625632 | Method and apparatus for square root generation using bit manipulation and instruction interleaving The invention provides improved methods and systems for generation of square roots of vector and administrative operands. The methods utilize bit-manipulation operations to halve intermediate values, generated by a processor reciprocal square root operati... | 09/23/2003 |
| 6567831 | Computer system and method for parallel computations using table approximation A method optimizes function evaluations performed by of a VLIW processor through enhanced parallelism by evaluating the function by table approximation using decomposition into a Taylor series.... | 05/20/2003 |
| 6385713 | Microprocessor with parallel inverse square root logic for performing graphics function on packed data elements An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executin... | 05/07/2002 |
| 6349319 | Floating point square root and reciprocal square root computation unit in a processor A method of computing a square root or a reciprocal square root of a number in a computing device uses a piece-wise quadratic approximation of the number. The square root computation uses the piece-wise quadratic approximation in the form: squareroot(X)=A... | 02/19/2002 |
| 6341300 | Parallel fixed point square root and reciprocal square root computation unit in a processor A parallel fixed-point square root and reciprocal square root computation uses the same coefficient tables as the floating point square root and reciprocal square root computation by converting the fixed-point numbers into a floating-point structure with ... | 01/22/2002 |
| 6175907 | Apparatus and method for fast square root calculation within a microprocessor An apparatus and method for calculating a square root of an operand in a microprocessor are provided. The microprocessor has a plurality of square root instructions, each of which specifies a square root calculation precision. The apparatus includes trans... | 01/16/2001 |
| 6108772 | Method and apparatus for supporting multiple floating point processing models A numerical processing method on a computer system in which an instruction having at least one operand and a type control is retrieved, and the operand is converted to a precision specified by the type control. The instruction is executed in the precision... | 08/22/2000 |
| 6078938 | Method and system for solving linear systems A system and method of using a computer processor (34) to generate a solution to a linear system of equations is provided. The computer processor (34) executes a Jacobi iterative technique to produce outputs representing the solution. Multiplication opera... | 06/20/2000 |
| 6067613 | Rotation register for orthogonal data transformation A data processing apparatus (71) includes a data processor bus (103), the rotation register (208) and a register selection circuit. The rotation register (208) is embodied by a plurality of data registers (200) each having a plurality of equal bit groups.... | 05/23/2000 |
| 6016538 | Method, apparatus and system forming the sum of data in plural equal sections of a single data word This invention is a technique for summing plural sections of a single data word. The technique uses a repeated process forming larger and larger partial sums. Initially the single data word is rotated one section. The original single data word and the rot... | 01/18/2000 |
| 5999960 | Block-normalization in multiply-add floating point sequence without wait cycles Described is a floating point processor comprising a multiply section and an add section, for performing a multiplication-add operation comprised of a multiplication operation prior to an addition operation which is using the result of the multiplication ... | 12/07/1999 |
| 5954789 | Quotient digit selection logic for floating point division/square root Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exac... | 09/21/1999 |
| 5931895 | Floating-point arithmetic processing apparatus A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit... | 08/03/1999 |
| 5847979 | Method and apparatus for generating an initial estimate for a floating point reciprocal of a square root An initial estimate of a reciprocal of a square root of a floating point number is generated by subtracting the input floating point number from a constant and shifting the results to the right by one bit. Additionally, the initial estimate of a reciproca... | 12/08/1998 |
| 5798955 | High-speed division and square root calculation unit A calculation unit speedily calculates a division or square root according to an iteration algorithm with a partial remainder expressed with the sum of a sum digit and carry digit. The calculation unit has a quotient selection logic circuit. The quotient ... | 08/25/1998 |
