Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 8095586 | Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away are described. Embodiments include transformations, code, state machines or other logic to perform a floating point operation on one or more floating ... | 01/10/2012 |
| 8069199 | Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest even Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest even are described. Embodiments include transformations, code, state machines or other logic to perform a floating point operation on one or more floating ... | 11/29/2011 |
| 8005884 | Relaxed remainder constraints with comparison rounding A system and method for efficient floating-point rounding in computer systems. A computer system may include at least one floating-point unit for floating-point arithmetic operations such as addition, subtraction, multiplication, division and square root. For the di... | 08/23/2011 |
| 7730117 | System and method for a floating point unit with feedback prior to normalization and rounding A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normal... | 06/01/2010 |
| 7725519 | Floating-point processor with selectable subprecision A floating-point processor with selectable subprecision includes a register configured to store a plurality of bits in a floating-point format, a controller, and a floating-point mathematical operator. The controller is configured to select a subprecision for a floa... | 05/25/2010 |
| 7720898 | Apparatus and method for adjusting exponents of floating point numbers A floating point unit, a central processing unit, and a method are provided for adjusting the exponent of a floating point number. During an addition or subtraction of two floating point numbers, the significand of the floating point result is rounded, and the expon... | 05/18/2010 |
| 7720899 | Arithmetic operation unit, information processing apparatus and arithmetic operation method An arithmetic operation unit, which generates information representing whether or not an arithmetic operation result has been shifted when the arithmetic operation result is normalized, has an arithmetic logical unit outputting the arithmetic operation result, a nor... | 05/18/2010 |
| 7676536 | Efficiently determining a floor for a floating-point number An apparatus, method and computer program product for processing a binary floating-point number having a sign bit and a mantissa having a fraction portion. It includes identifying the fraction portion of the binary floating-point number; and replacing each bit of th... | 03/09/2010 |
| 7373489 | Apparatus and method for floating-point exception prediction and recovery An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction... | 05/13/2008 |
| 7373369 | Advanced execution of extended floating-point add operations in a narrow dataflow A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the ... | 05/13/2008 |
| 7356553 | Data processing apparatus and method for determining a processing path to perform a data processing operation on input data elements The present invention provides a data processing apparatus and method for performing a data processing operation on first and second floating point data elements, the first floating point data element specifying a first exponent and the second floating point data el... | 04/08/2008 |
| 7353368 | Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, p... | 04/01/2008 |
| 7346642 | Arithmetic processor utilizing multi-table look up to obtain reciprocal operands Methods for determining the square root, reciprocal square root, or reciprocal of a number performed by a processor of a computer system. The methods produce high precision estimates without using iterative steps. In addition, the methods taught herein utilize compr... | 03/18/2008 |
| 7330867 | Method and device for floating-point multiplication, and corresponding computer-program product In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to ... | 02/12/2008 |
| 7330869 | Hybrid arithmetic logic unit Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a single-cycle ALU with the processing speed of a pipelined ALU. Arithmetic operations are performed in two stages: ... | 02/12/2008 |
| 7320117 | Design method for semiconductor integrated circuit device using path isolation A design method for a semiconductor integrated circuit device wherein for a path having a signal arrival time longer than a desired signal arrival time, and among multiple paths in the semiconductor integrated circuit device, a path isolation is performed so that a ... | 01/15/2008 |
| 7290027 | Circuit suitable for use in a carry lookahead adder An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits generate propagate, generate, and kill bits corresponding to at least a portion of the fir... | 10/30/2007 |
| 7236995 | Data processing apparatus and method for converting a number between fixed-point and floating-point representations A data processing apparatus and method for converting a number between fixed-point and floating-point representations. More particularly, the data processing apparatus includes a data processing unit operable to execute instructions, with the data processing unit be... | 06/26/2007 |
| 7231414 | Apparatus and method for performing addition of PKG recoded numbers An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a fi... | 06/12/2007 |
| 7212596 | Data detection circuit and method A data detection circuit and method detect a first bit that is the least significant among bits having a value 1 in N-bit input binary data and a second bit that is the second least significant among bits having the value 1 in the N-bit input data. The data detectio... | 05/01/2007 |
| 7197625 | Alignment and ordering of vector elements for single instruction multiple data processing The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit int... | 03/27/2007 |
| 7155471 | Method and system for determining the correct rounding of a function A method and system is used to determine the correct rounding of a floating point function. The method involves performing the floating point function to a higher precision than required and examining the portion of extra precision in the result known as the discrim... | 12/26/2006 |
| 7099910 | Partitioned shifter for single instruction stream multiple data stream (SIMD) operations A method of enabling a single instruction stream multiple data stream operation and a double precision floating point operation within a single floating point execution unit which includes providing a floating point unit with a two way aligner and a two way normaliz... | 08/29/2006 |
| 7069288 | Floating point system with improved support of interval arithmetic Embodiments consistent with the principles of the present invention provide improved results, compared to IEEE Std. 754, for floating point operations used in interval arithmetic calculations. One embodiment consistent with the principles of the present invention pr... | 06/27/2006 |
| 7069289 | Floating point unit for detecting and representing inexact computations without flags or traps A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a sep... | 06/27/2006 |
| 7062657 | Methods and apparatus for hardware normalization and denormalization Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of a cryptography accelerator coupled with a processor. Hardware normali... | 06/13/2006 |
| 7062525 | Circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method For use in a floating-point unit that supports floating-point formats having fractional parts of varying widths and employs a datapath wider than the fractional parts, a circuit and method for normalizing and rounding floating-point results and processor incorporati... | 06/13/2006 |
| 7058830 | Power saving in a floating point unit using a multiplier and aligner bypass The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coup... | 06/06/2006 |
| 7054898 | Elimination of end-around-carry critical path in floating point add/subtract execution unit A processor having a floating point execution unit with improved parallelism in the adder (add/subtract) unit is disclosed. A preferred aspect of the invention is a new use of the compare logic in the floating point execution unit, coupled with an end-around-carry b... | 05/30/2006 |
| 7047272 | Rounding mechanisms in processors An arithmetic unit, for example a multiply and accumulate (MAC) unit 42, for a processing engine includes a partial product reduction tree 480. The partial product reduction tree will generate carry results and provides a final output to a final adder ... | 05/16/2006 |
| 7043516 | Reduction of add-pipe logic by operand offset shift The shifters (30, 32) that a floating-point processor (10)'s addition pipeline (14) uses to align or normalize floating-point operands' mantissas before addition or subtraction shift a given mantissa pair one more bit to the left for subtraction... | 05/09/2006 |
| 7024052 | Motion image decoding apparatus and method reducing error accumulation and hence image degradation An Hadamard transform coding circuit changes a rounding method for each Hadamard transform block to prevent a rounding operation from providing an error biased in one direction, as seen in a picture in its entirety, for data compression and rounding. More specifical... | 04/04/2006 |
| 7024439 | Leading Zero Anticipatory (LZA) algorithm and logic for high speed arithmetic units Method and apparatus are described for anticipating the number of leading zeros or leading ones in a sum of mantissas irrespective of the sign of the result or the relative magnitudes of the input operands using a leading zero anticipation (LZA) device. An algorithm... | 04/04/2006 |
| 7010672 | Digital processor with programmable breakpoint/watchpoint trigger generation circuit A digital processor having a programmable breakpoint/watchpoint (BWP) trigger circuit that generates BWP triggers in response to user-defined combinations and/or sequences of trigger events. Several trigger event detection registers generate pre-trigger signals when... | 03/07/2006 |
| 7003539 | Efficiently determining a floor for a floating-point number An apparatus, method and computer program product for processing a binary floating-point number having a sign bit and a mantissa having a fraction portion. It includes identifying the fraction portion of the binary floating-point number; and replacing each bit of th... | 02/21/2006 |
| 7002980 | System and method for router queue and congestion management In a multi-QOS level queuing structure, packet payload pointers are stored in multiple queues and packet payloads in a common memory pool. Algorithms control the drop probability of packets entering the queuing structure. Instantaneous drop probabilities are obtaine... | 02/21/2006 |
| 6996596 | Floating-point processor with operating mode having improved accuracy and high performance Floating-point units (FPUs) and processors having a “flush-to-nearest” operating mode that provides improved accuracy over a conventional “flush-to-zero” mode. The FPU or processor includes an operand processing section and an operand flush section. For each... | 02/07/2006 |
| 6988120 | Arithmetic unit and method thereof A squaring multiplier for a floating-point number comprises: a pseudo carry generator for generating pseudo information concerning a carry equivalent to predetermined bits for the calculation of a target variable; an MSB look ahead circuit for employing the variable... | 01/17/2006 |
| 6978289 | Apparatus and method for minimizing accumulated rounding errors in coefficient values in a lookup table for interpolating polynomials An apparatus and method are disclosed for minimizing accumulated rounding errors in coefficient values in a lookup table for interpolating polynomials. Unlike prior art methods that individually round each polynomial coefficient of a function, the method of the pres... | 12/20/2005 |
| 6970897 | Self-timed transmission system and method for processing multiple data sets A self-timed transmission system and method are disclosed. An encoder encodes first and second data operands that are each defined on separate respective first and second sets of logic paths onto the same third set of logic paths by changing the encoding scheme. The... | 11/29/2005 |
