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Mountable Printable Placard With Headband
A resilient headband in a shape for being mounted on the head of the user. The headband is equipped with a longitudinal slotted member for holding a placard.
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| Number | Title | Issue Date |
| 7562106 | Multi-value digital calculating circuits, including multipliers Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and ap... | 07/14/2009 |
| 7433905 | Device and method for processing digital values in particular in non-adjacent form A table establishes correspondence between first sets of at least one number, expressed in accordance with a signed code where each number may have the value of 0, 1 or −1, and second sets of at least one number, expressed according to a simple form where each num... | 10/07/2008 |
| 7367119 | Method for forming a reinforced tip for a probe storage device Systems and methods in accordance with the present invention can include a tip contactable with a media. In an embodiment, the tip comprises a substantially hollow structure formed of a metal. The tip can be formed by depositing a first metal layer over silicon ther... | 05/06/2008 |
| 7336524 | Atomic probes and media for high density data storage A device in accordance with embodiments of the present invention comprises a contact probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the contact probe can include a silicon core having a conductive coating. Contact pro... | 02/26/2008 |
| 7309630 | Method for forming patterned media for a high density data storage device Systems in accordance with the present invention can include a tip contactable with a media, the media including a substrate and a plurality of cells disposed over the substrate, one or more of the cells being electrically isolated from the other of the cells by a m... | 12/18/2007 |
| 7301887 | Methods for erasing bit cells in a high density data storage device Methods in accordance with the present invention can be applied, in an embodiment, to a media comprising a phase change material to alter a resolved portion of the phase change material to have a resistance different from a resistance of the bulk material. A tip hav... | 11/27/2007 |
| 7257609 | Multiplier and shift device using signed digit representation The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware realization. By virtue thereof, it is enabled to use only one adder i... | 08/14/2007 |
| 7213043 | Sparce-redundant fixed point arithmetic modules A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A ... | 05/01/2007 |
| 7174358 | System, method, and apparatus for division coupled with truncation of signed binary numbers A system, method, and apparatus for dividing and truncating a dividend by a divisor, wherein the magnitude of the divisor is a positive power of two, e.g., 2x, is presented herein. If the divisor is positive, the sign bit of the dividend is concatenated x... | 02/06/2007 |
| 7165086 | System, method, and apparatus for division coupled with rounding of signed binary numbers A system, method, and apparatus for efficient rounding of signed numbers is presented herein. If the divisor is positive, the dividend is added to one half of the magnitude of the divisor. If the divisor is negative, the complement of the dividend is added to one ha... | 01/16/2007 |
| 7155474 | Current-mode multi-valued full adder in semiconductor device A full adder in a semiconductor device, includes a reference current generation unit for generating a reference current, a carry generation unit for generating a threshold current for generating a carry in response to the reference current and for generating the car... | 12/26/2006 |
| 7139786 | Method and apparatus for efficiently performing a square root operation One embodiment of the present invention provides a system that performs a carry-save square root operation that calculates an approximation of a square root, Q, of a radicand, R. The system calculates Q by iteratively selecting an operation to perform based on highe... | 11/21/2006 |
| 7106618 | Method of driving a non-volatile memory A method of driving a non-volatile memory which comprises a plurality of memory cells arranged in a two dimensional array, each having a field-effect transistor (1) whose gate and substrate are connected and a variable resistor element (2) comprising a... | 09/12/2006 |
| 7099851 | Applying term consistency to an equality constrained interval global optimization problem One embodiment of the present invention provides a system that solves a global optimization problem specified by a function ƒ and a set of equality constraints q1(x)=0 (i=1, . . . , r), wherein ƒ is a scalar function of a vector x=(x1, x... | 08/29/2006 |
| 6999941 | Providing gift clustering functionality to assist a user in ordering multiple items for a recipient A method and system for creating of gift clusters of multiple items in a client/server environment by users, and for the ordering of such user-defined gift clusters of multiple items. In particular, a user can specify multiple items to be associated together as a gi... | 02/14/2006 |
| 6978287 | DSP processor architecture with write datapath word conditioning and analysis An improved digital signal processing (DSP) processor architecture is presented in which word conditioning (e.g., rounding, saturation, etc.) and analysis operations (e.g., block floating point analysis) are implemented in the write datapath to memory. By moving wor... | 12/20/2005 |
| 6970994 | Executing partial-width packed data instructions A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectur... | 11/29/2005 |
| 6816877 | Apparatus for digital multiplication using redundant binary arithmetic A digital multiplication apparatus and method adopting redundant binary arithmetic is provided. In this digital multiplication apparatus, when two numbers X and Y are multiplied using a radix-2k number system, a data converter data-converts the m-bit number Y into m... | 11/09/2004 |
| 6671710 | Methods of computing with digital multistate phase change materials Non-binary methods of computing utilizing a digital multistate phase change material. Addition, subtraction, multiplication, and division are accomplished with the controlled application of energy to a phase change material. In one embodiment, energy in a... | 12/30/2003 |
| 6567835 | Method and apparatus for a 5:2 carry-save-adder (CSA) The present invention is a 5:2 carry-save-adder (CSA) that receives the five input signals I0, I1, I2, I3 and I4 and computes the two output signals SUM and CARRY. The 5:2 CSA comprises a first level of logic circuitry and a second level of logic circuitr... | 05/20/2003 |
| 6557021 | Rounding anticipator for floating point operations A method and apparatus that performs anticipatory rounding of intermediate results in a floating point arithmetic system while the intermediate results are being normalized is disclosed. One embodiment of the present invention includes four logic levels, ... | 04/29/2003 |
| 6546410 | High-speed hexadecimal adding method and system Adder circuitry is provided based on a reduced mathematical method to provide high-speed hexadecimal addition. A first adder adds the least significant binary digits of two hexadecimal numbers to provide a Digit1 and a Dot1, and a second adder adds the se... | 04/08/2003 |
| 6360241 | Computer method and apparatus for division and square root operations using signed digit The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient dig... | 03/19/2002 |
| 6347327 | Method and apparatus for N-nary incrementor The present invention is an incrementor that receives as inputs a 32-dit 1-of-4 operand and a 1-of-2 increment control signal. For each dit of the operand, the present invention determines whether the increment control signal, which is treated as a carry ... | 02/12/2002 |
| 6232894 | Reproducible data conversion and/or compression method of digital signals and a data converter and a digital computer HEN2, which is a combination of signals in which at least one of two adjacent digits at any digit position of one or more digits of a 2-based three digit redundant binary number with one signal of three digits {n, o, p} each expressing value {-1, 0, 1} as... | 05/15/2001 |
| 6223195 | Discrete cosine high-speed arithmetic unit and related arithmetic unit This arithmetic unit for carrying out partial sum of products for transform operations such as discrete cosine transform is provided which includes a plurality of first units for calculating in parallel sums of and/or differences between a plurality of in... | 04/24/2001 |
| 6223199 | Method and apparatus for an N-NARY HPG gate The present invention discloses an apparatus and method for performing carry propagate logic on two 1-of-4 two-bit addends to produce a 1-of-3 carry propagate indicator. The preferred embodiment of the present invention will set an H indicator for a given... | 04/24/2001 |
| 6219686 | Method and apparatus for an N-NARY sum/HPG adder/subtractor gate The present invention uses N-nary logic to perform addition or subtraction, along with carry propagate logic, within one gate. The gate produces as outputs a 1-of-4 result value and a 1-of-3 HPG indicator. The preferred embodiment of the present invention... | 04/17/2001 |
| 6219687 | Method and apparatus for an N-nary Sum/HPG gate The present invention utilizes N-nary logic to implement an add function and a carry-lookahead function within the same gate, producing an N-nary sum and an N-nary HPG indicator.... | 04/17/2001 |
| 6216146 | Method and apparatus for an N-nary adder gate The present invention discloses a method and apparatus for adding two 1-of-N addends to produce a 1-of-N sum. In the preferred embodiment, the addends and sum comprise 1-of-4 logic signals.... | 04/10/2001 |
| 6192387 | Multiple resonant tunneling circuits for signed digit multivalued logic operations Circuits containing resonant tunneling devices are disclosed which offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. Multivalued logic circuits implemented with resonant tunnel... | 02/20/2001 |
| 6073149 | Computational circuit A computational circuit for a multi-value addition comprising a parallel adder, an output adder, a quantizing portion and a logic conversion portion. Addition circuits in the above adders and thresholding circuits in the above quantizing portion consist o... | 06/06/2000 |
| 6047302 | Memory storing redundant binary codes and arithmetic unit and discrete cosine transformer using such memory A memory, which consumes less electric power and has a longer life, stores a redundant binary code produced by replacing each digit of data in binary representation, with a separate 2-bit string allocated to a value which the digit can take. If a value to... | 04/04/2000 |
| 6029185 | Discrete cosine high-speed arithmetic unit and related arithmetic unit An arithmetic unit for carrying out partial sum of products for transform operations such as discrete cosine transform is provided which includes a plurality of first units for calculating in parallel sums of and/or differences between a plurality of inpu... | 02/22/2000 |
| 5999962 | Divider which iteratively multiplies divisor and dividend by multipliers generated from the divisors to compute the intermediate divisors and quotients A divider which multiplies both divisor and dividend by a first multiplier generated from the divisor to compute an intermediate divisor and an intermediate quotient, and iterates such computations by the number of times needed, so that the intermediate d... | 12/07/1999 |
| 5917742 | Semiconductor arithmetic circuit A semiconductor arithmetic circuit which realizes multiple-item addition processing at high speed and with a small surface areas The semiconductor arithmetic circuit adds a plurality of data expressed in binary format which is provided with terminals for ... | 06/29/1999 |
| 5822233 | Digital arithmetic calculator and digital computer using non-redundant (2N+1) notation system with a radix of (2N+1) A central processing unit and a digital data processing system for performing arithmetic processing of numbers that are not presented using traditional 10 radix signed digits 0, 1, 2 . . . 9. The central processing unit and digital data processing system ... | 10/13/1998 |
| 5815422 | Computer-implemented multiplication with shifting of pattern-product partials A constant multiplication device is designed for multiplying a received binary multiplicand by a constant multiplier which, when expressed in binary or signed-digit notation, includes a repeated pattern with three or more non-zero values. The device inclu... | 09/29/1998 |
| 5815420 | Microprocessor arithmetic logic unit using multiple number representations A microprocessor (5) having at least one arithmetic logic unit, or ALU, (42) for operating upon operands of multiple number representation types is disclosed. The ALU (42) includes a binary logical unit (52) for performing logical operations upon operands... | 09/29/1998 |
| 5767476 | Manufacturing method for automotive frame An automotive frame is assembled by joining fins of extrusions formed of aluminum alloy by resistance spot welding. The fins are formed integrally with each extrusion by extrusion. Alternatively, the extrusions may be joined together through a node part h... | 06/16/1998 |
