Bizarre Patents
Process For Propelling Foodstuffs or the Like into a Crowd
A method of launching foodstuffs into a crowd for promotional and entertainment purposes.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8176109 | Calculating unit for reducing an input number with respect to a modulus A calculating unit for reducing an input number with respect to a modulus, wherein the input number has input number portions of different significances, wherein the input number portions represent the input number with respect to a division number, wherein the modu... | 05/08/2012 |
| 8135767 | Standard cell for arithmetic logic unit and chip card controller A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second ... | 03/13/2012 |
| 8117251 | Computation of a multiplication operation with an electronic circuit and method A computing method and circuit for computing a modular operation with at least one operand having a binary representation. Iteratively for each bit of this operand, doubling the value of an intermediate result stored in a first memory element by shifting the bits of... | 02/14/2012 |
| 8112467 | Computationally efficient mathematical engine A method and apparatus perform many different types of algorithms that utilizes a calculation unit capable of utilizing the same multipliers for different algorithms. The calculation unit preferably includes a processor that has a plural number of arithmetic logic u... | 02/07/2012 |
| 8065356 | Datapipe synchronization device A programmable element for data processing comprises a crosspoint switch (318), a mathematical operation module (320), and a plurality of data hold modules (604,606). Each of the data hold modules (604,606) receives data from the crosspoi... | 11/22/2011 |
| 8051122 | SIMD arithmetic device capable of high-speed computing A general-purpose register file including a plurality of general-purpose registers stores parallel arithmetic data. A plurality of pattern registers store a plurality of items of pattern data indicating the rearrangement of data in bytes, in half words, in words, or... | 11/01/2011 |
| 7991816 | Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the resul... | 08/02/2011 |
| 7970810 | Nanoelectronics A circuit element includes a plurality of computation blocks connected at least partially in series for processing multi-bit numbers. Each of the computation blocks includes a plurality of transistors having characteristic threshold voltages. The circuit element is ... | 06/28/2011 |
| 7958179 | Arithmetic method and device of reconfigurable processor Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a mu... | 06/07/2011 |
| 7949700 | Modal interval processor A logic circuit computes various modal interval (MI) arithmetic values using a plurality of arithmetic function units (AFUs), each dedicated to compute a specific MI arithmetic operation. The AFUs receive first and second MI operand values each encoded in first and ... | 05/24/2011 |
| 7921148 | Standard cell for arithmetic logic unit and chip card controller A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second ... | 04/05/2011 |
| 7917566 | Arithmetic device capable of obtaining high-accuracy calculation results A plurality of general-purpose registers each has a first bit width. A computing unit has a first and a second input end, at least the first input end having a second bit width wider than the first bit width, and performs an arithmetical operation on data supplied f... | 03/29/2011 |
| 7882165 | Digital signal processing element having an arithmetic logic unit A digital signal processing circuit including: a multiplier circuit; a plurality of multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit coupled to plurality of multiplexers and controlled by a second opcode. | 02/01/2011 |
| 7865542 | Digital signal processing block having a wide multiplexer A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithm... | 01/04/2011 |
| 7853634 | Digital signal processing circuit having a SIMD circuit An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled ... | 12/14/2010 |
| 7844653 | Digital signal processing circuit having a pre-adder circuit A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder c... | 11/30/2010 |
| 7840627 | Digital signal processing circuit having input register blocks An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block couple... | 11/23/2010 |
| 7725518 | Work-efficient parallel prefix sum algorithm for graphics processing units One embodiment of the present invention sets forth a technique for computing a parallel prefix sum using one or more cooperative thread arrays (CTA) within a graphics processing unit. The prefix sum input list is partitioned and distributed to each CTA. Within each ... | 05/25/2010 |
| 7711762 | Efficient computation for eigenvalue decomposition and singular value decomposition of matrices For eigenvalue decomposition, a first set of at least one variable is derived based on a first matrix being decomposed and using Coordinate Rotational Digital Computer (CORDIC) computation. A second set of at least one variable is derived based on the first matrix a... | 05/04/2010 |
| 7660841 | Flexible accumulator in digital signal processing circuitry A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cy... | 02/09/2010 |
| 7610325 | System(s), method(s), and apparatus for detecting end of slice groups in a bitstream Presented herein are system(s), method(s), and apparatus for detecting end of slice groups in a video bitstream. In one embodiment, there is presented a circuit for extracting a data structure from one or more data words. The circuit comprises a multiplexer, a bit p... | 10/27/2009 |
| 7590677 | Processor with summation instruction using overflow counter Performing a sum of numbers operation in a variable bit-length environment of a processor in response to a summation instruction, comprising a) adding a least significant portion (LSP) of a first number to a LSP of another number from a plurality of numbers, wherein... | 09/15/2009 |
| 7548942 | Base four processor A digital signal processing system which samples an analog voltage, converts the sample to a multi digit base four number, performs a computation with this number, using base four arithmetic, and converts the result back to an analog voltage. This system is comprise... | 06/16/2009 |
| 7516171 | Arithmetic unit and method for data storage and reading An arithmetic unit includes a memory, an arithmetic logic unit, a register and a combining circuit. The arithmetic logic unit executes a predetermined arithmetic operation with respect to the data read from memory. The register temporarily stores the data read from ... | 04/07/2009 |
| 7509365 | Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the resul... | 03/24/2009 |
| 7496620 | Calculation apparatus A calculation apparatus outputting a calculation result in accordance with an input condition and capable of increasing the processing speed. As a data of an address corresponding to an input condition of an calculation formula, its calculation result is stored in a... | 02/24/2009 |
| 7428565 | Logical operation circuit and logical operation device To provide a logical operation circuit and a logical operation device which can performs a logical operation using a ferroelectric capacitor. The area ratio between the ferroelectric capacitors CF1 and CF2 are set such that the potential difference Vde... | 09/23/2008 |
| 7426529 | Processor and method for a simultaneous execution of a calculation and a copying process A processor includes a source register having a source register content, a destination register, a calculating unit for performing a calculation using the source register content, wherein the calculation is performed in several calculation cycles, and wherein in eac... | 09/16/2008 |
| 7424503 | Pipelined accumulators Pipelined digital accumulators. Parallel digital accumulators for use in digital signal processing are improved through pipelining. An accumulator is partitioned into a plurality of pipelined stages, and the pipeline delay is used to reduce the effect of carry propa... | 09/09/2008 |
| 7421465 | Arithmetic early bypass A value that bypasses some of the computations for an arithmetic operation can be supplied for performance of a dependent arithmetic operation without waiting for completion of the computations of the arithmetic operation. During performance of a first arithmetic op... | 09/02/2008 |
| 7412474 | Montgomery modular multiplier using a compressor and multiplication method A Montgomery modular multiplier receiving a multiplicand (A), a modulus (M), and a multiplier (B), using a t-s compressor, where t>3 and s>1, and a multiplication method performed in the same. In response to a carry propagation adder signal, the t-s compressor perfo... | 08/12/2008 |
| 7395294 | Arithmetic logic unit An arithmetic logic unit is provided. The arithmetic logic unit preferably includes a minimum of routing delays. An arithmetic logic unit according to the invention preferably receives a plurality of operands from a plurality of operand registers, performs an arithm... | 07/01/2008 |
| 7392272 | Calculation device and calculation method An arithmetic unit and an arithmetic method that output no information necessary for decryption or encryption to the outside and can perform a self-protecting function when an illegal attack is made. A command monitoring part (44) monitors input command seque... | 06/24/2008 |
| 7389416 | Method of verifiably sharing a secret in potentially asynchronous networks In accordance with the present invention, there is provided a method for sharing a secret value x among n participating network devices via an asynchronous network. The n participating network devices comprises t faulty devices and k sub-devices capable of reconstru... | 06/17/2008 |
| 7380099 | Apparatus and method for an address generation circuit A method and apparatus for an address generation circuit. In one embodiment, the method includes computing a carry-in for at least one group of a predetermined number of bits of a propagate and a generate signal formed from a plurality of logical address components.... | 05/27/2008 |
| 7373369 | Advanced execution of extended floating-point add operations in a narrow dataflow A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the ... | 05/13/2008 |
| 7363478 | Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruc... | 04/22/2008 |
| 7363466 | Microcomputer A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 | 04/22/2008 |
| 7360220 | Methods and apparatus for multi-threading using differently coded software segments to perform an algorithm Methods and apparatus for multi-threading on a simultaneous multi-threading processor are provided. The methods and apparatus described herein increase computational throughput by launching two or more computational threads to perform the same algorithm using two di... | 04/15/2008 |
| 7352275 | Device for comparing two words of n bits each The disclosure relates to a device for comparing two words, N and P, of n bits each. The device includes at least one comparator block comprising n basic comparator blocks which can each be used to compare bits Ni and Pi of digit place i of words N and P, whereby 0=... | 04/01/2008 |
