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| Number | Title | Issue Date |
| 7917559 | Configurable IC's with configurable logic circuits that perform adder and/or subtractor operations An integrated circuit (IC) is disclosed that includes a set of configurable logic circuits. Each configurable logic circuit configurably performs a set of functions. A particular configurable circuit receives configuration data defining a function for the particular... | 03/29/2011 |
| 7853632 | Architectural floorplan for a digital signal processing circuit A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of f... | 12/14/2010 |
| 7353516 | Data flow control for adaptive integrated circuitry The present invention concerns data flow control in adaptive integrated circuitry which utilizes a data flow model for data processing. The present invention controls task initiation and execution based upon data consumption measured in data buffer units. In the var... | 04/01/2008 |
| 7328377 | Error correction for programmable logic integrated circuits Systems and methods for detecting and correcting errors in programmable logic ICs are provided. In one embodiment, a scrubber periodically reads the memory cells in a programmable logic IC, detects and corrects any errors, and writes the corrected contents back into... | 02/05/2008 |
| 7310757 | Error detection on programmable logic resources Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compare... | 12/18/2007 |
| 7240263 | Apparatus for performing stuck fault testings within an integrated circuit An apparatus for performing stuck fault testings within an integrated circuit is disclosed. A delay chain structure includes a first select register, a second select register, a decoder and a chain of multiplexors. With a set of select signals, the first select regi... | 07/03/2007 |
| 7216139 | Programmable logic device including multipliers and configurations thereof to reduce resource utilization In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and ca... | 05/08/2007 |
| 7205791 | Bypass-able carry chain in a programmable logic device A carry chain in a logic array block includes a first path connecting a first series of logic elements in the logic array block, where the logic elements in the first series is a subset of the set of logic elements in the logic array block. The carry chain also incl... | 04/17/2007 |
| 7203714 | Logic circuit A CMOS logic circuit is disclosed wherein the number of kinds of basic parts is suppressed to five to allow designing of a circuit which operates at a high speed and repetitiveness of wiring lines is increased to allow designing of a circuit which is simple in circu... | 04/10/2007 |
| 7196541 | Electronic circuit with array of programmable logic cells An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an inpu... | 03/27/2007 |
| 7193433 | Programmable logic block having lookup table with partial output signal driving carry multiplexer A programmable logic block provides to a carry chain multiplexer an output signal representing a partial output signal from a programmable lookup table (LUT), e.g., an output signal having a value that depends upon fewer than all of the data input signals of the LUT... | 03/20/2007 |
| 7164288 | Electronic circuit with array of programmable logic cells An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic mode. The programmable logic units are coupled in parallel between an inpu... | 01/16/2007 |
| 7157934 | Programmable asynchronous pipeline arrays High-performance, highly pipelined asynchronous FPGAs employ a very fine-grain pipelined logic block and routing interconnect architecture. These FPGAs, which do not use a clock to sequence computations, automatically “self-pipeline” their logic without the desi... | 01/02/2007 |
| 7135887 | Programmable logic device multispeed I/O circuitry Programmable logic device integrated circuitry having I/O circuitry portions having different maximum speed capabilities and different amounts of programmability for supporting various I/O signaling standards is provided. High-speed I/O circuitry and low-speed I/O c... | 11/14/2006 |
| 7100025 | Apparatus and method for performing single-instruction multiple-data instructions An apparatus and method for performing single-instruction multiple-data instructions using a single multiply-accumulate unit while minimizing operational latency. The multiply-accumulate unit generates a first half and a second half of a data result. A register stor... | 08/29/2006 |
| 7072212 | String programmable nonvolatile memory with NOR architecture A nonvolatile memory with a memory array arranged in rows and columns of memory cells in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines and a column decoder. The column decoder comprises a plurality o... | 07/04/2006 |
| 7047166 | Method and VLSI circuits allowing to change dynamically the logical behavior A method, named the product terms method that allows to implement and/or to change dynamically the logical behavior of any combinational or synchronous sequential circuits has been presented. The method uses for every product term of logical equations, expressed as ... | 05/16/2006 |
| 7035886 | Re-configurable combinational logic device A re-configurable combinational logic device. The device comprises combinational logic that inputs a number of signals and a memory array for storing data to define Boolean expressions for a number of states. The states have Boolean expressions of selected signals o... | 04/25/2006 |
| 7007264 | System and method for dynamic reconfigurable computing using automated translation A system (20) for dynamic reconfigurable computing includes at least one microprocessor implemented on a field programmable gate array (10) having a programmable fabric (12). The system can include a predefined interface (42) between an e... | 02/28/2006 |
| 6996709 | Method for configuring a configurable hardware block by configuring configurable connections provided around a given type of subunit A method for configuring a configurable hardware block includes implementing commands and/or command sequences of a program to be executed. The implementing step includes ascertaining a given type of subunit of a configurable hardware block, the given type of subuni... | 02/07/2006 |
| 6993616 | Read-write interface system and method that accesses a leading bit in advance of a read operation A read-write interface system and method for a peripheral device includes storing data to be processed by a peripheral device; receiving a set of input data bits; transferring the set of input data bits from the shift register to the latch circuit in a write operati... | 01/31/2006 |
| 6959316 | Dynamically configurable processor A data processor, such as a DSP, includes a multiplier block having a multiplier front end for generating partial products from input operands, and further includes a plurality of ALUs having inputs that are switchably or programmably coupled, in a first mode of ope... | 10/25/2005 |
| 6954395 | String programmable nonvolatile memory with NOR architecture A nonvolatile memory with a memory array arranged in rows and columns of memory cells in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines and a column decoder. The column decoder comprises a plurality o... | 10/11/2005 |
| 6938223 | Logic circuit having a functionally redundant transistor network A method and system for constructing, designing, and using a family of logic circuits based on methods of interconnecting transistors (or more generally, switches). The method includes the selective use of functionally redundant transistors to achieve target objecti... | 08/30/2005 |
| 6873181 | Automated implementation of non-arithmetic operators in an arithmetic logic cell Disclosed is a method of freeing up a non-arithmetic logic block by configuring an LE driving the non-arithmetic logic block to carry out the non-arithmetic logic function of the non-arithmetic logic block. Appropriately configured LEs are identified and the LEs are... | 03/29/2005 |
| 6754686 | Literal sharing method for fast sum-of-products logic A method and apparatus for implementing fast sum-of-products logic in a Field Programmable Gate Array (FPGA) is disclosed. The method includes literal-sharing decomposition of the sum-of-products logic to reduce the number of configurable logic block (CLB) slices re... | 06/22/2004 |
| 6732126 | High performance datapath unit for behavioral data transmission and reception A programmable and configurable datapath unit (DPU) includes a configuration of single-bit multi-function processing units (PUs). The DPU can perform any of a variety of functions depending on the control applied to each PU. Functionality can be increased by utilizi... | 05/04/2004 |
| 6704816 | Method and apparatus for executing standard functions in a computer system using a field programmable gate array A computer system comprising mass storage, a system bus connected to the mass storage, and a processor unit connected to the system bus. A library of standard functions is stored in the mass storage. Each library function is stored in at least one of two ... | 03/09/2004 |
| 6625721 | Registers for 2-D matrix processing A processor has at least two sets of registers. The first set stores a matrix of data, and the second set stores a transposed copy of the matrix of data. When any portion of any row of the first set is modified, the corresponding portion of the column of ... | 09/23/2003 |
| 6573749 | Method and apparatus for incorporating a multiplier into an FPGA One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, du... | 06/03/2003 |
| 6553395 | Reconfigurable processor devices The invention relates to a reconfigurable device comprising a plurality of processing devices, a connection matrix providing an interconnect between the processing devices, and means to define the configuration of the connection matrix. Each of the proces... | 04/22/2003 |
| 6539477 | System and method for control synthesis using a reachable states look-up table A system and method of implementing thereof that maps and condenses system control using reachable state control words is described. The system includes a control logic block, a look-up table which stores N-bit reachable state control words derived from a... | 03/25/2003 |
| 6476634 | ALU implementation in single PLD logic cell Structures and methods that implement an ALU (Arithmetic Logic Unit) circuit in a PLD (Programmable Logic Device) while using only one PLD logic cell to implement a one-bit ALU circuit. The ALU circuit has two data input signals and two operator input sig... | 11/05/2002 |
| 6449628 | Apparatus and method for programmable datapath arithmetic arrays A programmable data arithmetic array includes a set of data buses and a matrix of data arithmetic units including fixed function units and programmable function units connected to the set of data buses. Bidirectional interconnect is positioned between the... | 09/10/2002 |
| 6404227 | Apparatus and method for interleaving a signal carry chain in an integrated circuit An interleaved signal carry structure includes a first signal line and a second signal line forming a first bus. A third signal line and a fourth signal line form a second bus. A first set of carry function generators are positioned between the first sign... | 06/11/2002 |
| 6353841 | Reconfigurable processor devices The invention relates to a reconfigurable device comprising a plurality of processing devices, a connection matrix providing an interconnect between the processing devices, and means to define the configuration of the connection matrix. Each of the proces... | 03/05/2002 |
| 6311200 | Reconfigurable program sum of products generator A reconfigurable programmable sum of products generator allows for multiple configurations to be associated with a programmable sum of products generator. These configurations can be modified by changing the configurations in an associated configuration m... | 10/30/2001 |
| 6209077 | General purpose programmable accelerator board A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dyna... | 03/27/2001 |
| 6188240 | Programmable function block A programmable function block comprises a core logic circuit having a first argument input group consisting of first through fourth argument input terminals, a second argument input group consisting of first through fourth argument input terminals, first ... | 02/13/2001 |
| 6119048 | Integrated circuit for processing digital signal A digital signal process of a plurality of functions is enabled by a common hardware constructed on one chip having input terminals t1, t2 and t2'; output terminals t3 and t4; and a control signal input terminal t5. The chip is constructed to include clas... | 09/12/2000 |
